2 Avoiding SSN Problems

SSN problems can be reduced or completely avoided by including SSOs as a design parameter from the early stages of a system design. As an FPGA is a programmable device, the I/O configuration parameters, such as voltage compliance and slew rate, are not selected until the FPGA I/O buffers are configured and programmed. This gives the designer a lot of flexibility in making design adjustments to solve system-level signal integrity issues, such as GND bounce and VCC bounce.

Few recommendations that save time and effort are as follows:

  • Identify potential SSOs and spread them around the package.

  • Avoid placement of asynchronous pins (resets, enables, and so on) near SSOs. Place SSOs away from clock pins/traces.

  • Decouple VCC/GND pairs to filter out noise. When possible, use low slew outputs.

  • Low pass filters can be used to meter out the glitches at the PCB level. Whenever possible, create synchronous designs that are glitch tolerant.

  • Use 5V CMOS-compliant inputs when possible, as they have better noise margin.

  • Increased capacitive load decreases the amplitude of the GND bounce by reducing the output slew rate.

  • The switching outputs can be made to switch in a staggered fashion by inserting delays in the design so that the switching is not simultaneous. This can be achieved by inserting the Microchip macro BUFD to force buffer delays. Even if the system layout is fixed, this method can help reduce SSN as no board changes are necessary.