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IEEE® 802.11 b/g/n Link Controller Module ATWILC1000-MR110xB
Introduction
Features
1 Ordering Information and Module Marking
2 Functional Overview
3 Pinout and Package Information
4 Electrical Specifications
4.1 Absolute Ratings
4.2 Recommended Operating Conditions
4.3 DC Electrical Characteristics
4.4 Receiver Performance
4.5 Transmitter Performance
4.6 Timing Characteristics
5 Power Management
5.1 Current Consumption in Various Device States
5.2 Restrictions for Power States
5.3 Power-Up/Down Sequence
5.4 Digital I/O Pin Behavior During Power-Up Sequences
6 CPU and Memory Subsystems
6.1 Processor
6.2 Memory Subsystem
6.3 Nonvolatile Memory (eFuse)
7 WLAN Subsystem
7.1 MAC
7.2 PHY
7.3 Radio
8 External Interfaces
8.1 Interfacing with the Host Microcontroller
8.2 SPI Client Interface
8.3 SDIO Client Interface
8.4 UART Debug Interface
8.5 I2C Client Interface
9 Notes on Interfacing with the ATWILC1000-MR110xB
10 Reference Design
11 Module Outline Drawings
12 Design Consideration
12.1 ATWILC1000-MR110PB Placement and Routing Guidelines
12.2 Printed PCB Antenna Performance of ATWILC1000-MR110PB
12.3 ATWILC1000-MR110UB Placement and Routing Guidelines
12.4 Recommended External Antennas
12.5 Reflow Profile Information
12.6 Module Assembly Considerations
12.7 Conformal Coating
13 Appendix A: Regulatory Approval
13.1 United States
13.2 Canada
13.3 Europe
13.4 Japan
13.5 Korea
13.6 Taiwan
13.7 China
13.8 Other Regulatory Information
14 Reference Documentation
15 Document Revision History
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