3.27.4 Clock Generator (CLOCK)

The Clock system generates and distributes the clock for the processor and peripherals

Clock Generators:

  • A low-power 32.768 kHz crystal oscillator

  • A low-power embedded 64 kHz (typical) RC oscillator generating the 32 kHz source clock

  • A 8 to 24 MHz crystal oscillator or a 12 to 48 MHz XRCGB crystal resonator with Bypass mode

  • A 12 MHz embedded RC oscillator

  • A 480 MHz UTMI PLL providing a clock for the USB High-speed Device Controller

  • A 600 to 1200 MHz programmable PLL (input from 8 to 50 MHz), provides the clock to the processor and to the peripherals

  • A 700 MHz fractional-N programmable audio PLL, with 22-bit frequency resolution and two independent programmable post dividers to drive the CLK_AUDIO output pin and the internal peripherals (AUDIOPLLCLK)

Clock Distribution:

  • Master clock controller sources processor clock controller and generates Master Clock (MCK) which is the processor dependent clock to all peripherals

  • Processor clock controller implements IDLE mode for processor clock

  • Matrix clock controller controls the clocks to the bus matrices

  • Programmable clock controller controls outputting clock to external pins

  • Peripheral clock controller controls processor dependent clock to all peripherals

  • Generic clock controller controls processor independent clocks to peripherals that support it

  • LCD, ISC, DDR and USB host clock controllers control the processor independent clocks to those peripherals

Using The Library

The Clock peripheral library initializes the clock system as configured by the user in the MCC Clock configurator. It can be accessed via the "Tools" drop down of the MPLAB Code Configurator menu bar.

Library Interface

Clock Generator peripheral library provides the following interfaces:

Functions

NameDescription
CLK_InitializeInitializes hardware of the System Clock and Peripheral Clock
CLK_UTMIPLLEnableEnables UTMI PLL clock
CLK_UTMIPLLDisableDisables UTMI PLL clock