3.25.2 Advanced Interrupt Controller (AIC)
Controls the Interrupt Lines (nIRQ and nFIQ) of an ARM Processor
128 Individually Maskable and Vectored Interrupt Sources
Source 0 is reserved for the fast interrupt input (FIQ)
Programmable edge-triggered or level-sensitive internal sources
Programmable rising/falling edge-triggered or high/low level-sensitive external sources
8-level Priority Controller
Drives the normal interrupt of the processor
Handles priority of the interrupt sources 1 to 127
Higher priority interrupts can be served during service of lower priority interrupt
Vectoring
Optimizes interrupt service routine branch and execution
One 32-bit vector register for all interrupt sources
Interrupt vector register reads the corresponding current interrupt vector
General Interrupt Mask
Provides processor synchronization on events without triggering an interrupt
Register Write Protection
Using The Library
The AIC peripheral library initializes interrupt controller as configured by the user in the MCC. User can launch the AIC configurator using the "Tools" drop down in MCC menu bar. Using the AIC configurator, user can enable interrupt, configure priority, interrupt type and interrupt vector name.
NOTE: Only the interrupts of type non secure can be configured. Software routing of interrupts between secure and non-secure domains are not supported
Library Interface
Advanced Interrupt Controller peripheral library provides the following interfaces:
Functions
Name | Description |
---|---|
AIC_INT_Initialize | Initializes Advanced Interrupt Controller (AIC) peripheral library |
AIC_INT_IrqEnable | Enable Processor interrupt |
AIC_INT_IrqDisable | Disable Processor interrupt |
AIC_INT_IrqRestore | Restore processor interrupt state |