1.3 DMA

Direct Memory Access (DMA) is a subsystem that can transfer data between different memory regions, including register memory, without CPU intervention. This feature allows data to be transferred between peripherals with a much lower CPU overhead in comparison to transferring the data without DMA. DMA can be beneficial in applications that require data to be transferred at rates close to the clock frequency of the device, such as in this Arbitrary Waveform Generator application.

The DMA module is comprised of a DMA controller and multiple interface channels that allows data transfer between the device memory regions. The System Arbiter is used to allocate priority levels for different system events, and can be used to give a DMA higher priority than main code execution or even ISR execution. The DMA subsystem operates on an independent data and address bus which allows data to be transferred with no impact on CPU operation (assuming the DMA has been configured to have a lower priority than the CPU using the System Arbiter).

The transfer process can be configured to be triggered by various system events. For instance, a DMA can be configured to automatically transfer a message received by a UART to a user-defined storage buffer when the UART receive interrupt is triggered.

Each DMA channel has its own configurable priority level, which can be set using the System Arbiter. By default, DMA has lower priority than the CPU lowest priority and will only execute during holes in CPU execution due to two-cycle instructions, such as GOTO. The DMA can be configured to pause CPU execution when triggered, or to even pause interrupt execution, depending on the priority set using the System Arbiter.