25.3.3.1.3.2 Clock Generation

Being a master device in a synchronous communication interface, the USART in Master SPI mode must generate the interface clock to be shared with the slave devices. The interface clock is generated using the fractional Baud Rate Generator, which is described in 25.3.2.2.1 The Fractional Baud Rate Generator.

Each Data bit is transmitted by pulling the data line high or low for one full clock period. The receiver will sample bits in the middle of the transmitter hold period as shown in the figure below. It also shows how the timing scheme can be configured using the Inverted I/O Enable (INVEN) bit in the PORTx.PINnCTRL register and the USART Clock Phase (UCPHA) bit in the USARTn.CTRLC register.

Figure 25-5. Data Transfer Timing Diagrams

The table below further explains the figure above.

Table 25-2. Functionality of INVEN and UCPHA Bits
INVEN UCPHA Leading Edge (1) Trailing Edge (1)
0 0 Rising, sample Falling, transmit
0 1 Rising, transmit Falling, sample
1 0 Falling, sample Rising, transmit
1 1 Falling, transmit Rising, sample
Note:
  1. The leading edge is the first clock edge of a clock cycle. The trailing edge is the last clock edge of a clock cycle.