When performing a multi-byte transfer (LD combined with
REPEAT), or reading out the System Information Block (SIB), the
output data will come out in a continuous stream. Depending on the application, on the
receiver side, the data might come out too fast, and there might not be enough time for
the data to be processed before the next Start bit arrives.
The inter-byte delay works by inserting a fixed number of Idle bits for
multi-byte transfers. The reason for adding an inter-byte delay is that there is no
guard time inserted when all data is going in the same direction.
The inter-byte delay feature can be enabled by writing a
‘1’ to the Inter-Byte Delay Enable (IBDLY) bit in the Control A
(UPDI.CTRLA) register. As a result, two extra Idle bits will be inserted between each
byte to relax the sampling time for the debugger.Figure 34-19. Inter-Byte Delay Example with
LD and RPT
Note:
GT denotes the guard time
insertion.
SB is for Stop bit.
IB is the inserted inter-byte delay.
The rest of the frames are data and instructions.
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
