23.3.3.1 Register Synchronization Categories
Most of the I/O registers need to be synchronized to the TCD core clock domain. This is done differently for different register categories.
| Enable and Command Registers | Double-Buffered Registers | Static Registers | Read-Only Registers | Normal I/O Registers |
|---|---|---|---|---|
| TCDn.CTRLA (ENABLE bit) | TCDn.DLYCTRL | TCDn.CTRLA(1) (All bits except ENABLE bit) | TCDn.STATUS | TCDn.INTCTRL |
| TCDn.CTRLE | TCDn.DLYVAL | TCDn.CTRLB | TCDn.CAPTUREA | TCDn.INTFLAGS |
| TCDn.DITCTRL | TCDn.CTRLC | TCDn.CAPTUREB | ||
| TCDn.DITVAL | TCDn.CTRLD | |||
| TCDn.DBGCTRL | TCDn.EVCTRLA | |||
| TCDn.CMPASET | TCDn.EVCTRLB | |||
| TCDn.CMPACLR | TCDn.INPUTCTRLA | |||
| TCDn.CMPBSET | TCDn.INPUTCTRLB | |||
| TCDn.CMPBCLR | TCDn.FAULTCTRL(2) |
- The bits in the Control A (TCDn.CTRLA) register are enable-protected, except the
ENABLE bit. They can only be written when ENABLE is written to ‘
0’ first. - This register is protected by the Configuration Change Protection Mechanism, requiring a timed write procedure for changing its value settings.
Enable and Command Registers
Because of the synchronization between the clock domains, it is only
possible to change the ENABLE bit in the Control A (TCDn.CTRLA) register, while the
Enable Ready (ENRDY) bit in the Status (TCDn.STATUS) register is
‘1’.
The Control E (TCDn.CTRLE) register is automatically synchronized to the
TCD core domain when the TCD is enabled and as long as no synchronization is ongoing
already. Check if the Command Ready (CCMDRDY) bit in TCDn.STATUS is ‘1’
to ensure that it is possible to issue a new command. TCDn.CTRLE is a strobe register
that will clear itself when the command is sent.
Double-Buffered Registers
The double-buffered registers can be updated in normal I/O writes, while TCD
is enabled and no synchronization between the two clock domains is ongoing. Check that
the CMDRDY bit in TCDn.STATUS is ‘1’ to ensure that it is possible to
update the double-buffered registers. The values will be synchronized to the TCD core
domain when a synchronization command is sent or when TCD is enabled.
| Synchronization Issuing Bit | Double Register Update |
|---|---|
| CTRLC.AUPDATE | Every time the CMPBCLRH register is written, the synchronization occurs at the end of the TCD cycle. |
| CTRLE.SYNC (1) | Occurs once, as soon as the SYNC bit is synchronized with the TDC domain. |
| CTRLE.SYNCEOC (1) | Occurs once at the end of the next TCD cycle. |
- If synchronization is already ongoing, the action has no effect.
Static Registers
Static registers cannot be updated while TCD is enabled. Therefore, these
registers must be configured before enabling TCD. To see if TCD is enabled, check if
ENABLE in TCDn.CTRLA is read as ‘1’.
Normal I/O and Read-Only Registers
Normal I/O and read-only registers are not constrained by any synchronization between the domains. The read-only registers inform about synchronization status and values synchronized from the core domain.