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SAMA5D2 System in Package (SiP) Silicon Errata and Data Sheet Clarifications SAMA5D2 SIP Family Silicon Errata and Data Sheet Clarifications
SAMA5D2 System in Package (SIP)
1 Silicon Issue Summary
2 Power Supply
2.1 VDDSDMMC power supply over-consumption
3 Flexible Serial Communication Controller (FLEXCOM)
3.1 FLEXCOM SMBUS alert signalling is not functional
4 Ethernet MAC (GMAC)
4.1 Bad association of timestamps and PTP packets
4.2 Screening registers not working
5 Inter-IC Sound Controller (I2SC)
5.1 I2SC first sent data corrupted
6 Controller Area Network (MCAN)
6.1 Flexible data rate feature does not support the ISO 16845-1:2016 CRC
6.2 Needless activation of interrupt MCAN_IR.MRAF
6.3 Return of receiver from Bus Integration state after Protocol Exception Event
6.4 Message RAM/RAM Arbiter not responding in time
6.5 Data loss (payload) in case storage of a received frame has not completed until end of EOF field is reached
6.6 Edge filtering causes mis-synchronization when falling edge at Rx input pin coincides with end of integration phase
6.7 Configuration of MCAN_NBTP.NTSEG2 = ’0’ not allowed
6.8 Retransmission in DAR mode due to lost arbitration at the first two identifier bits
6.9 Tx FIFO message sequence inversion
6.10 Unexpected High Priority Message (HPM) interrupt
6.11 Issue message transmitted with wrong arbitration and control fields
6.12 Debug message handling state machine not reset to Idle state when CCCR.INIT is set
6.13 Frame transmitted despite confirmed transmit cancellation for CAN-FD messages with more than 8 data bytes
7 Peripheral Touch Controller (PTC)
7.1 Wrong pull-up value on PD[18:3] during reset
8 Power Management Controller (PMC)
8.1 Change of the field PMC_MCKR.PRES is not allowed if Master/Processor Clock Prescaler frequency is too high
9 Pulse Width Modulation Controller (PWM)
9.1 Fault Protection to Hi-Z for PWMx output not functional
10 Quad Serial Peripheral Interface (QSPI)
10.1 QSPI hangs with long DLYCS
11 Real-Time Clock (RTC)
11.1 RTC_SR.TDERR flag is stuck at 0
11.2 Read access truncated to the first 24 bits for register RTC_TIMALR (UTC_MODE)
12 ROM Code
12.1 UART blocks USB connection to SAM-BA Monitor
12.2 JTAG_TCK on IOSET 4 pin has a wrong configuration after boot
12.3 Secure Boot Mode: AES-RSA X.509 Certificate Serial Number Length Limit
13 Secure Digital MultiMedia Card Controller (SDMMC)
13.1 Software 'Reset For all' command may not execute properly
13.2 Sampling clock tuning procedure
13.3 SDMMC I/O calibration does not work
14 Secure Fuse Controller (SFC)
14.1 Fuse matrix programming requires a main clock (MAINCK) frequency between 10 and 15 MHz
14.2 Fuse matrix read requires a main clock (MAINCK) frequency below 28 MHz
15 Synchronous Serial Controller (SSC)
15.1 Unexpected delay on TD output
16 Two-wire Interface (TWIHS)
16.1 The TWI/TWIHS Clear command does not work
17 Watchdog Timer (WDT)
17.1 Restart command of WDT may reset the DDR controller
18 Data Sheet Clarifications
18.1 SAMA5D2 SiP
18.2 SAMA5D2
19 Revision History
19.1 Rev. G - 08/2022
19.2 Rev. F - 03/2022
19.3 Rev. E - 09/2021
19.4 Rev. D - 03/2021
19.5 Rev. C - 02/2020
19.6 Rev. B - 01/2020
19.7 Rev. A - 04/2019
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