15.6.8 Peripheral Interrupt Flag Status and Clear C

This flag is cleared by writing a one to the flag.

This flag is set when a Peripheral Access Error occurs while accessing the peripheral associated with the respective INTFLAGC bit, and will generate an interrupt request if INTENSET.ERR is one.

Writing a zero to this bit has no effect.

Writing a one to this bit will clear the corresponding INTFLAGC interrupt flag.

Name:	INTFLAGC
Offset:	0x1C
Reset:	0x000000
Property:	Secure


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
			TRAM	OPAMP	I2S	CCL	TRNG	PTC
Access			RW/-/RW	RW/-/RW	RW/-/RW	RW/-/RW	RW/-/RW	RW/-/RW
Reset			0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	DAC	ADC	TCC3	TCC2	TCC1	TCC0	TC2	TC1
Access	RW/-/RW	RW/-/RW	RW/-/RW	RW/-/RW	RW/-/RW	RW/-/RW	RW/-/RW	RW/-/RW
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	TC0	SERCOM5	SERCOM4	SERCOM3	SERCOM2	SERCOM1	SERCOM0	EVSYS
Access	RW/-/RW	RW/-/RW	RW/-/RW	RW/-/RW	RW/-/RW	RW/-/RW	RW/-/RW	RW/-/RW
Reset	0	0	0	0	0	0	0	0

Bit 21 – TRAM Interrupt Flag for TRAM

15.6.8 Peripheral Interrupt Flag Status and Clear C

Bit 21 – TRAM Interrupt Flag for TRAM

Bit 20 – OPAMP Interrupt Flag for OPAMP

Bit 19 – I2S Interrupt Flag for I2S

Bit 18 – CCL Interrupt Flag for CCL

Bit 17 – TRNG Interrupt Flag for TRNG

Bit 16 – PTC Interrupt Flag for PTC

Bit 15 – DAC Interrupt Flag for DAC

Bit 14 – ADC Interrupt Flag for ADC

Bits 10, 11, 12, 13 – TCC Interrupt Flag for TCCn [n = 3..0]

Bits 7, 8, 9 – TC Interrupt Flag for TCn [n = 2..0]

Bits 1, 2, 3, 4, 5, 6 – SERCOM Interrupt Flag for SERCOMn [n = 5..0]

Bit 0 – EVSYS Interrupt Flag for EVSYS