49.20 DAC Module Electrical Specifications

Table 49-24. DAC Module Electrical Specifications
AC CHARACTERISTICS				Standard Operating Conditions: VDD = AVDD = 1.62V to 3.63V (unless otherwise stated) Operating temperature: -40°C ≤ T_A ≤ +85°C for Industrial
Param. No.	Symbol	Characteristics		Min.	Typ.	Max.	Units	Conditions
DAC_1	D_RES	DAC Resolution		—	—	12	Bits	—
DAC_3	D_CLK	Internal DAC Clock Frequency (f_{GCLK_DAC})		—	—	FCLK_53	MHz	FCLK_53: Refer to Maximum Clock Frequencies Electrical Specifications
DAC_5	D_SAMP	DAC Sampling Rate	Low Power (DACCTRLx.CCTRL=0x0)	0.05	—	0.1	MSPS	+/-4 LSB of final value for step size≤100 LSB @ C_LOAD & R_LOAD w/AVDD=3.3V
DAC_5	D_SAMP	DAC Sampling Rate	High Power (DACCTRLx.CCTRL=0x2)	0.1	—	1	MSPS
DAC_7	V_OUT	Output Voltage Linear Range		AVSS+0.15	—	AVDD-0.15	V	Ext Pin (Buffered) VREF=AVDD @ C_LOAD & R_LOAD
				AVSS+0.15	—	VREF		Ext Pin (Buffered) @ C_LOAD & R_LOAD (VREF < (AVDD-150mV))
				AVSS	—	VREF		Internal (no buffer)
DAC_9	V_REF ⁽⁶⁾	DAC Reference Input Option	REFSEL = VREFAB CTRLB.REFSEL = 0x2	2.4V	—	AVDD-0.15	V	External Reference VREFAB (buffered) VREF bypass Cap = 10 nF
			REFSEL = VREFAU CTRLB.REFSEL = 0x0		—	AVDD		External Reference VREFAU (unbuffered) VREF bypass Cap = 10 nF
			REFSEL = INTREF CTRLB.REFSEL = 0x3		VR_1 VR_3	AVDD-0.15		Internal Reference VR_1, VR_3: Refer to Internal Voltage Reference Electrical Specifications
			REFSEL = AVDD CTRLB.REFSEL = 0x1	AVDD				—
DAC_11	C_LOAD	DAC Out max load to meet V_OUT& T_SET		—	—	50	pF	—
DAC_13	R_LOAD	DAC Out max load to meet V_OUT & T_SET		5	—	—	kΩ	—
DAC_15	T_SET ⁽⁴⁾	DAC Settling Time	Low Power Mode (DACCTRLx.CCTRL = 0)	—	—	1/D_SAMPmin+1	µs	+/-4LSB of final value for step size≤100 LSB @ C_LOAD & R_LOAD w/ AVDD=3.3V
DAC_15	T_SET ⁽⁴⁾	DAC Settling Time	High Performance Mode (DACCTRLx.CCTRL = 2)	—	—	1/D_SAMPmin+1	µs
DAC_17	T_SET_FS ⁽⁴⁾	DAC Full Scale Settling Time	Low Power Mode (DACCTRLx.CCTRL = 0)	—	—	7/D_SAMPmin+1	µs	+/-4 LSB of final value for step size from 10% to 90% @ C_LOAD & R_LOAD w/ AVDD=3.3V
DAC_17	T_SET_FS ⁽⁴⁾	DAC Full Scale Settling Time	High Performance Mode (DACCTRLx.CCTRL = 2)	—	—	7/D_SAMPmin+1	µs
DIFFERENTIAL MODE^(2,3,6)
DDAC_19	INL	Integral Non Linearity	REFSEL = AVDD CTRLB.REFSEL = 0x1	-2.5	-	2.5	LSB	AVDD=3.3V w/ C_LOAD & R_LOAD High Power Mode (DACCTRLx.CCTRL=2) (Max sampling rate 1MSPS) A clipping value of 150mV is applied to both RampStart and RampEnd in the DAC Linearity calculation according to DAC_7 parameter.
			REFSEL = VREFAU (2.5V) CTRLB.REFSEL = 0x0	-2.9	-	2.5
			REFSEL = VREFAB (2.5V) CTRLB.REFSEL = 0x2	-2.1	-	2.1
			REFSEL = INTREF (2.4V) CTRLB.REFSEL = 0x3	-5.1	-	5.0
DDAC_21	DNL	Differential Non Linearity	REFSEL = AVDD CTRLB.REFSEL = 0x1	-2.3	-	1.0	LSB
			REFSEL = VREFAU (2.5V) CTRLB.REFSEL = 0x0	-2.6	-	2.7
			REFSEL = VREFAB (2.5V) CTRLB.REFSEL = 0x2	-2.1	-	1.2
			REFSEL = INTREF (2.4V) CTRLB.REFSEL = 0x3	-6.4	-	5.9
DDAC_23	G_ERR	Gain Error	REFSEL = AVDD CTRLB.REFSEL = 0x1	-31.8	-	-18.2	LSB
			REFSEL = VREFAU (2.5V) CTRLB.REFSEL = 0x0	-31.9	-	-16.4
			REFSEL = VREFAB (2.5V) CTRLB.REFSEL = 0x2	-37.8	-	-17.6
			REFSEL = INTREF (2.4V) CTRLB.REFSEL = 0x3	-105.8	-	59.2
DDAC_25	E_OFF	Offset Error	REFSEL = AVDD CTRLB.REFSEL = 0x1	4.9	-	15.2	LSB
			REFSEL = VREFAU (2.5V) CTRLB.REFSEL = 0x0	-1.6	-	16.8
			REFSEL = VREFAB (2.5V) CTRLB.REFSEL = 0x2	4.3	-	19.1
			REFSEL = INTREF (2.4V) CTRLB.REFSEL = 0x3	-34.0	-	51.9
DDAC_27	ENOB ⁽⁵⁾	Effective Number of Bit	REFSEL = AVDD CTRLB.REFSEL = 0x1	10.0	-	10.9	Bits	AVDD=3.3V w/ C_LOAD & R_LOAD. Digital sine magnitude: 0x080 to 0xF7F High Power Mode (DACCTRLx.CCTRL=2) (Max sampling rate 1MSPS)
			REFSEL = VREFAU (2.5V) CTRLB.REFSEL = 0x0	10.7	-	12.5
			REFSEL = VREFAB (2.5V) CTRLB.REFSEL = 0x2	10.6	-	12.3
			REFSEL = INTREF (2.4V) CTRLB.REFSEL = 0x3	9.6	-	11.2
DDAC_29	SNR ⁽⁵⁾	Signal To Noise Ratio	REFSEL = AVDD CTRLB.REFSEL = 0x1	72.1	-	79.0	dB
			REFSEL = VREFAU (2.5V) CTRLB.REFSEL = 0x0	72.5	-	78.1
			REFSEL = VREFAB (2.5V) CTRLB.REFSEL = 0x2	71.6	-	78.7
			REFSEL = INTREF (2.4V) CTRLB.REFSEL = 0x3	59.9	-	69.8
DDAC_31	THD ^(1,5)	Total Harmonic Distortion	REFSEL = AVDD CTRLB.REFSEL = 0x1	-68.0	-	-62.4	dB
			REFSEL = VREFAU (2.5V) CTRLB.REFSEL = 0x0	-85.2	-	-67.6
			REFSEL = VREFAB (2.5V) CTRLB.REFSEL = 0x2	-80.3	-	-66.8
			REFSEL = INTREF (2.4V) CTRLB.REFSEL = 0x3	-82.5	-	-67.3
SINGLE ENDED MODE^(2,3,6)
SDAC_19	INL	Integral Non Linearity	REFSEL = AVDD CTRLB.REFSEL = 0x1	-3.4	-	3.2	LSB	AVDD=3.3V w/ C_LOAD & R_LOAD High Power Mode (DACCTRLx.CCTRL=2) (Max sampling rate 1MSPS) A clipping value of 150mV is applied to both RampStart and RampEnd in the DAC Linearity calculation according to DAC_7 parameter.
			REFSEL = VREFAU (2.5V) CTRLB.REFSEL = 0x0	-5.1	-	4.7
			REFSEL = VREFAB (2.5V) CTRLB.REFSEL = 0x2	-4.4	-	4.2
			REFSEL = INTREF (2.4V) CTRLB.REFSEL = 0x3	-12.3	-	8.2
SDAC_21	DNL	Differential Non Linearity	REFSEL = AVDD CTRLB.REFSEL = 0x1	-3.7	-	2.7	LSB
			REFSEL = VREFAU (2.5V) CTRLB.REFSEL = 0x0	-4.8	-	5.1
			REFSEL = VREFAB (2.5V) CTRLB.REFSEL = 0x2	-3.6	-	3.3
			REFSEL = INTREF (2.4V) CTRLB.REFSEL = 0x3	-13.0	-	11.3
SDAC_23	G_ERR	Gain Error	REFSEL = AVDD CTRLB.REFSEL = 0x1	-38.4	-	-19.1	LSB
			REFSEL = VREFAU (2.5V) CTRLB.REFSEL = 0x0	-39.8	-	-19.8
			REFSEL = VREFAB (2.5V) CTRLB.REFSEL = 0x2	-45.3	-	-20.6
			REFSEL = INTREF (2.4V) CTRLB.REFSEL = 0x3	-111.9	-	53.8
SDAC_25	E_OFF	Offset Error	REFSEL = AVDD CTRLB.REFSEL = 0x1	3.5	-	16.8	LSB
			REFSEL = VREFAU (2.5V) CTRLB.REFSEL = 0x0	4.9	-	22.2
			REFSEL = VREFAB (2.5V) CTRLB.REFSEL = 0x2	8.7	-	26.4
			REFSEL = INTREF (2.4V) CTRLB.REFSEL = 0x3	8.7	-	27.4
SDAC_27	ENOB ⁽⁵⁾	Effective Number of Bit	REFSEL = AVDD CTRLB.REFSEL = 0x1	9.9	-	11.0	Bits	AVDD=3.3V w/ C_LOAD & R_LOAD. Digital sine magnitude: 0x080 to 0xF7F High Power Mode (DACCTRLx.CCTRL=2) (Max sampling rate 1MSPS)
			REFSEL = VREFAU (2.5V) CTRLB.REFSEL = 0x0	9.8	-	11.3
			REFSEL = VREFAB (2.5V) CTRLB.REFSEL = 0x2	9.7	-	11.2
			REFSEL = INTREF (2.4V) CTRLB.REFSEL = 0x3	8.7	-	10.2
SDAC_29	SNR ⁽⁵⁾	Signal To Noise Ratio	REFSEL = AVDD CTRLB.REFSEL = 0x1	65.7	-	76.0	dB
			REFSEL = VREFAU (2.5V) CTRLB.REFSEL = 0x0	63.6	-	75.5
			REFSEL = VREFAB (2.5V) CTRLB.REFSEL = 0x2	63.6	-	75.5
			REFSEL = INTREF (2.4V) CTRLB.REFSEL = 0x3	55.0	-	65.0
SDAC_31	THD ^(1,5)	Total Harmonic Distortion	REFSEL = AVDD CTRLB.REFSEL = 0x1	-68.9	-	-62.4	dB
			REFSEL = VREFAU (2.5V) CTRLB.REFSEL = 0x0	-71.2	-	-63.3
			REFSEL = VREFAB (2.5V) CTRLB.REFSEL = 0x2	-70.5	-	-62.8
			REFSEL = INTREF (2.4V) CTRLB.REFSEL = 0x3	-70.6	-	-62.6
Note: Value taken over 7 harmonics. 12-bit mode. Over V_OUT range defined by DAC_7 parameter. Assuming DAC is configured and that first conversion is done. Characterized with 1kHz sine wave. DAC functional device operation with external VREF < 2.4V is guaranteed, but not characterized. DAC will function, but with degraded performance. DAC accuracy is limited by users application noise/accuracy on AVDD, AVSS and VREF accuracy/drift.