35.1 Overview

The serial peripheral interface (SPI) is one of the available modes in the Serial Communication Interface (SERCOM).

The SPI uses the SERCOM transmitter and receiver configured as shown in Block Diagram. Each side, host and client, depicts a separate SPI containing a shift register, a transmit buffer and a receive buffer.

The transmitter consists of a 8-bytes write FIFO buffer, a Shift register, and control logic for different frame formats. The write buffer support data transmission without any delay between frames.

The receiver consists of a 8-bytes receive FIFO buffer and a Shift register. Status information of the received data is available for error checking. Data and clock recovery units ensure robust synchronization and noise filtering during asynchronous data reception.

In addition, the SPI host uses the SERCOM baud-rate generator, while the SPI client can use the SERCOM address match logic. Labels in capital letters are synchronous to CLK_SERCOMx_APB and accessible by the CPU, while labels in lowercase letters are synchronous to the SCK clock.