35.2 Features

  • Full-duplex, four-wire interface (MISO, MOSI, SCK, SS)
  • Receive buffer: 8-bytes FIFO
  • Transmit buffer: 8-bytes FIFO
  • Supports all four SPI modes of operation
  • Single data direction operation allows alternate function on MISO or MOSI pin
  • Selectable LSB-first data transfer or MSB-first data transfer
  • DMA operations supported
  • 32-bit Extension for better system bus utilization
  • Host operation:
    • Serial clock speed, fSCK=1/tSCK(1)
    • 8-bit clock generator
    • Hardware controlled SS
  • Client operation:
    • Serial clock speed, fSCK = 1/tSSCK(1)
    • Optional 8-bit address match operation
    • Operation in all sleep modes
    • Wake on SS transition