10.2.3.2 PIC32CM LS00 Boot Configuration Row

Table 10-20. PIC32CM LS00 BOCOR Bitfields Definition
Bit Pos.NameUsageValue (1)Related Peripheral Register
18:0ReservedReservedAll 1sReserved
27:19BNSCNon-Secure Callable Flash (BOOT region) Size = BNSC*0x20 0x000IDAU.SCFGB
31:28ReservedReservedAll 1sReserved
39:32BOOTOPTBoot Option0x00Boot ROM
50:40BOOTPROTBoot Protection size = BOOTPROT*0x1000x000IDAU.SCFGB
51SECCFGLOCKSecurity Configuration Lock0x1Boot ROM
52DICEENDICE Enable0x0Boot ROM
55:53ReservedReservedAll 1sReserved
56BCWENBoot Configuration Write Enable0x1NVMCTRL.SCFGB
57BCRENBoot Configuration Read Enable0x1NVMCTRL.SCFGB
63:58ReservedReservedAll 1sReserved
95:64BOCORCRCBoot Configuration CRC for bit 63:00xc0349accBoot ROM
127:96ReservedReservedAll 1sReserved
255:128CEKEY0Chip Erase Key 0All 1sBoot ROM
383:256CEKEY1Chip Erase Key 1All 1sBoot ROM
511:384CEKEY2Chip Erase Key 2All 1sBoot ROM
639:512CRCKEYCRC KeyAll 1sBoot ROM
895:640BOOTKEYSHA- or HMAC-based Secure Boot KeyAll 1sBoot ROM
1151:896UDS (2)DICE UDS KeyAll 1s (unless provisioned)(2)Boot ROM
1791:1152ReservedReservedAll 1sReserved
2047:1792BOCORHASHBoot Configuration Row HashAll 1sBoot ROM
Note:
  1. Fresh from Factory Value or after a ChipErase_ALL command.
  2. UDS must be provisioned if DICE is enabled (BOCOR.DICEEN=1). A ChipErase_ALL (CE2) will reset these bits to All 1s. Refer to DICE section in Boot ROM chapter for more information.
Table 10-21. PIC32CM LS00 BOCOR Mapping
OffsetBit

Pos.

Name
0x00-0x115:0Reserved
0x0223:16BNSCReserved
0x0331:24ReservedBNSC
0x0439:32BOOTOPT
0x0547:40BOOTPROT
0x0655:48ReservedDICEENSECCFGLOCKBOOTPROT
0x0763:56ReservedBCRENBCWEN
0x08-0x0B95:64BOCORCRC
0x0C-0x0F127:96Reserved
0x10-0x1F255:128CEKEY0
0x20-0x2F383:256CEKEY1
0x30-0x3F511:384CEKEY2
0x40-0x4F639:512CRCKEY
0x50-0x6F895:640BOOTKEY
0x70-0x8F1151:896UDS
0x90-0xDF1791:1152Reserved
0xE0-0xFF2047:1792BOCORHASH