32.6.7 Ready Users
Important: For PIC32CM LS00/LS60 Non-Secure accesses, read
accesses (R*) are allowed only if the security attribution for the corresponding
channel (CHANNELx) is set as Non-Secured in the NONSECCHAN register.
| Name: | READYUSR |
| Offset: | 0x1C |
| Reset: | 0x000000FF |
| Property: | Mix-Secure |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| READYUSR7 | READYUSR6 | READYUSR5 | READYUSR4 | READYUSR3 | READYUSR2 | READYUSR1 | READYUSR0 | ||
| Access | R/R*/R | R/R*/R | R/R*/R | R/R*/R | R/R*/R | R/R*/R | R/R*/R | R/R*/R | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
Bits 0, 1, 2, 3, 4, 5, 6, 7 – READYUSRn Ready User for Channel n
This bit is set when all event users connected to channel n are ready to handle incoming events on channel n.
This bit is cleared when at least one of the event users connected to the channel is not ready.
When the event channel n path is asynchronous, this bit is always read zero.