35.7.3 Control C

Bits 31:30 – TXTRHOLD[1:0] Transmit FIFO Threshold

These bits define the threshold for generating the Data Register Empty interrupt and DMA TX trigger.


Value	Name	Description
0	DEFAULT	Interrupt and DMA triggers can be generated as long as the FIFO is not full.
1	HALF	Interrupt and DMA triggers are generated when half FIFO space is free.
2	EMPTY	Interrupt and DMA triggers are generated when the FIFO is empty.
3	-	Reserved

These bits define the threshold for generating the RX Complete interrupt and DMA RX trigger.


Value	Name	Description
0	DEFAULT	Interrupt and DMA triggers can be generated when a DATA is present in the FIFO.
1	HALF	Interrupt and DMA triggers can be generated only when the FIFO is half-full.
2	FULL	Interrupt and DMA triggers can be generated only when the FIFO is full.
3	-	Reserved

This bit enables the FIFO operation.

Value	Description
0	FIFO operation is disabled
1	FIFO operation is enabled

This bit enables 32-bit Extension for read and write transactions to the DATA register.

When disabled, access is according to CTRLB.CHSIZE.

Value	Description
0	Transactions from and to DATA register are 8-bit
1	Transactions from and to DATA register are 32-bit

When non-zero, CTRLC.ICSPACE selects the minimum number of baud cycles the SCK line will not toggle between characters.

Value	Description
0x00	Inter-Character Spacing is disabled
0x01-0x3F	The minimum Inter-Character Spacing

Name:	CTRLC
Offset:	0x08
Reset:	0x00000000
Property:	PAC Write-Protection, Enable-Protected