10.1.6.3.2 QSPI Timings

For the QSPI0 instance, the timings shown in the tables below are provided in the following domains:
  • 1.8V domain: VDDQSPI from 1.7V to 1.9V, maximum external capacitor: 10 pF, Drive = 1, Slewrate = 0
  • 3.3V domain: VDDQSPI from 3.0V to 3.6V, maximum external capacitor: 10 pF, Drive = 0, Slewrate = 0
Table 10-23. QSPI Timings in Single Data Rate Mode (STR)
SymbolParameterConditionsMinMaxUnit
fQSCKQSCK maximum frequency––100MHz
QSPI0QIOx data in to QSCK falling edge (input setup time)–1–ns
QSPI1QIOx data in to QSCK falling edge (input hold time)–1–ns
QSPI2QSCK falling edge to QIOx delay–01ns
Table 10-24. QSPI Timings in Double Data Rate Mode (DTR)
SymbolParameterConditionsMinMaxUnit
fQSPIQSCK operating frequency––57.7MHz
tQSCK_MINMinimum SPCK period–17.3–ns
QSPI6CS low before QSCK edge (rising or falling)(1)–1.1–ns
QSPI7QSCK edge (rising or falling) to CS high(2)–0.21ns
QSPI8QIOx input data setup to QSCK edge (rising or falling)–1.4–ns
QSPI9QIOx input data hold after QSCK edge (rising or falling)–0.9–ns
QSPI10QSCK edge (rising or falling) to QIOx delay–00.7ns
Note:
  1. Refer to DLYCS and DLYBS descriptions in Quad Serial Peripheral Interface (QSPI) for more configuration details.
  2. Refer to DLYBCT description in Quad Serial Peripheral Interface (QSPI) for more configuration details.
Table 10-25. QSPI Timings in DTR Mode with Data Strobe (DQS)
SymbolParameterConditionsMinMaxUnit
fQSPIQSCK operating frequency––100MHz
tQSCK_MINMinimum SPCK period–10–ns
QSPI11CS low before QSCK edge (rising or falling)(1)–1.1–ns
QSPI12QSCK edge (rising or falling) to CS high(2)–0.21ns
QSPI13QIOx input skew to DQS edge (rising or falling)–02.2ns
QSPI14QSCK edge (rising or falling) to QIOx delay–0tQSCK/4 + 0.7ns
Note:
  1. Refer to DLYCS and DLYBS descriptions in Quad Serial Peripheral Interface (QSPI) for more configuration details.
  2. Refer to DLYBCT description in Quad Serial Peripheral Interface (QSPI) for more configuration details.