2.1 Arm926EJ-S Processor

The Arm926EJ-S processor is a member of the Arm9™ family of general-purpose microprocessors. The Arm926EJ-S implements Arm architecture version 5TEJ and is targeted at multi-tasking applications where full memory management, high performance, low die size and low power are important features.

The Arm926EJ-S processor supports the 32-bit Arm and 16-bit Thumb instruction sets, enabling the user to trade off between high performance and high code density. It also supports the 8-bit Java instruction set and includes features for efficient execution of Java bytecode, providing a Java performance similar to JITs (Just-In-Time compilers), for the next generation of Java-powered wireless and embedded devices. It includes an enhanced multiplier design for improved DSP performance.

The Arm926EJ-S processor supports the Arm debug architecture and includes logic to assist in both hardware and software debug.

The Arm926EJ-S provides a complete high performance processor subsystem, including:
  • an Arm9EJ-S™ integer core,
  • a Memory Management Unit (MMU),
  • separate instruction and data AMBA AHB bus interfaces,
  • a 32-Kbyte L1 instruction cache and a 32-Kbyte data cache.

For information on the Arm926EJ-S processor, refer to the ARM926EJ-S Technical Reference Manual on www.arm.com.