8.2.153 GMAC Screening Type 2 Rate Limit Register x
This register manages the traffic policing function relevant to the 802.1Qci standard and associated to type 2 screener.
| Name: | GMAC_SCR2_RATE_LIMITx |
| Offset: | 0x0B40 + x*0x04 [x=0..7] |
| Reset: | 0x00000000 |
| Property: | R/W |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| MAX_RATE_VAL[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| MAX_RATE_VAL[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| INTERVAL_TIME[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| INTERVAL_TIME[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:16 – MAX_RATE_VAL[15:0] Maximum Rate Value for the Interval Time
Defines the maximum number of bytes the type 2 screener is permitted to match in the programmed interval time.
Bits 15:0 – INTERVAL_TIME[15:0] Interval Time for Maximum Rate Checking
Defines the period for which the total number of bytes of received frames matched by the screener are accumulated and compared with the value configured in MAX_RATE_VAL. When the value exceeds MAX_RATE_VAL, then the current frame and frames subsequently matched will dropped until an interval time passes where MAX_RATE_VAL is not exceeded. When MAX_RATE_VAL=0, then no rate limiting will be performed. The interval time is specified in units of 64 receive clock periods.