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Arm® Arm926EJ-S™ Processor-Based MPU, 800 MHz, MIPI DSI® or CSI-2, LVDS, RGB, 2D Graphics, Gigabit Ethernet with TSN, CAN-FD, Octal/Quad SPI, Crypto, PUF
Arm® Arm926EJ-S™ Processor-Based MPU, 800 MHz, MIPI DSI® or CSI-2, LVDS, RGB, 2D Graphics, Gigabit Ethernet with TSN, CAN-FD, Octal/Quad SPI, Crypto, PUF
Product Pages
SAM9X70 SAM9X72 SAM9X75
  1. Home
  2. 9 Connectivity Subsystem
  3. 9.3 Flexible Serial Communication Controller (FLEXCOM)
  4. 9.3.7 USART Functional Description
  5. 9.3.7.8 LIN Mode
  6. 9.3.7.8.5 Character Reception
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  • Introduction
  • Reference Document
  • 1 Overview
  • 2 CPU and Interconnect
  • 3 Memories
  • 4 System Controller
  • 5 Analog Subsystem
  • 6 Image Subsystem
  • 7 Audio Subsystem
  • 8 Security and Cryptography Subsystem
  • 9 Connectivity Subsystem
    • 9.1 Overview
    • 9.2 Ethernet MAC (GMAC)
    • 9.3 Flexible Serial Communication Controller (FLEXCOM)
      • 9.3.1 Description
      • 9.3.2 Embedded Characteristics
      • 9.3.3 Block Diagram
      • 9.3.4 I/O Lines Description
      • 9.3.5 Product Dependencies
      • 9.3.6 Register Accesses
      • 9.3.7 USART Functional Description
        • 9.3.7.1 Baud Rate Generator
        • 9.3.7.2 Receiver and Transmitter Control
        • 9.3.7.3 Synchronous and Asynchronous Modes
        • 9.3.7.4 ISO7816 Mode
        • 9.3.7.5 IrDA Mode
        • 9.3.7.6 RS485 Mode
        • 9.3.7.7 USART Comparison Function on Received Character
        • 9.3.7.8 LIN Mode
          • 9.3.7.8.1 Modes of Operation
          • 9.3.7.8.2 Baud Rate Configuration
          • 9.3.7.8.3 Receiver and Transmitter Control
          • 9.3.7.8.4 Character Transmission
          • 9.3.7.8.5 Character Reception
          • 9.3.7.8.6 Header Transmission (Host Node Configuration)
          • 9.3.7.8.7 Header Reception (Client Node Configuration)
          • 9.3.7.8.8 Client Node Synchronization
          • 9.3.7.8.9 Identifier Parity
          • 9.3.7.8.10 Node Action
          • 9.3.7.8.11 Response Data Length
          • 9.3.7.8.12 Checksum
          • 9.3.7.8.13 Frame Slot Mode
          • 9.3.7.8.14 LIN Errors
          • 9.3.7.8.15 LIN Frame Handling
          • 9.3.7.8.16 LIN Frame Handling with the DMA
          • 9.3.7.8.17 Wakeup Request
          • 9.3.7.8.18 Bus Idle Timeout
        • 9.3.7.9 LON Mode
        • 9.3.7.10 Test Modes
        • 9.3.7.11 USART FIFOs
        • 9.3.7.12 16-bit Data Protocol Support
        • 9.3.7.13 USART Register Write Protection
      • 9.3.8 SPI Functional Description
      • 9.3.9 TWI Functional Description
      • 9.3 Register Summary
    • 9.4 Quad Serial Peripheral Interface (QSPI)
    • 9.5 Secure Digital MultiMedia Card Controller (SDMMC)
    • 9.6 Controller Area Network (MCAN)
    • 9.7 Timer Counter (TC)
    • 9.8 Pulse Width Modulation Controller (PWM)
  • 10 USB Subsystem
  • 11 Electrical and Mechanical Characteristics
  • 12 Revision History
  • Microchip Information

9.3.7.8.5 Character Reception

See Receiver Operations.

DS60001813E

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.

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