2.3.1 Software Reset of the QSPI NOR Flash Memory
- raising the 4 I/O lines to high level during 12 QSPI clock cycles
- sending a software Reset command sequence (66h, 99h)
before sending any other SPI command.
Step 1 causes the QSPI NOR Flash memory to exit its Continuous Read (XIP) mode, regardless of its manufacturer, whereas step 2 restores the Power-on Reset state, hence exiting the stateful 4-Byte Address mode.
Since the ROM code does not know the internal state of the QSPI NOR Flash memory (has it entered its SPI 4-4-4 mode?) when it tries to reset this memory, the ROM code first sends the reset command sequence (66h, 99h) with the SPI 4-4-4 protocol, to force an exit from the SPI 4-4-4 mode if needed, then sends the same reset command sequence but with the SPI 1-1-1 protocol. If the QSPI NOR Flash memory has not entered its SPI 4-4-4 mode, it should ignore the first Reset command sequence as it cannot decode it correctly.