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Ultra-Low-Power Arm® Cortex®-A5 Core-Based MPU, 500 MHz, Graphics Interface, Ethernet 10/100, CAN, USB, PCI 5.0 Pre-Certified SAMA5D2 Series
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46
Flexible Serial Communication Controller (FLEXCOM)
46.7
USART Functional Description
46.7.3
Synchronous and Asynchronous Modes
SAMA5D2 Series
Introduction
Features
Description
1
Configuration Summary
2
Block Diagram
3
Signal Description
4
Microchip Recommended Power Management Solutions
5
Safety and Security Features
6
Package and Pinout
7
Power Considerations
8
Memories
9
Event System
10
System Controller
11
Peripherals
12
Chip Identifier (CHIPID)
13
Cortex-A5 Processor (ARM)
14
L2 Cache Controller (L2CC)
15
Debug and Test Features
16
Standard Boot Strategies
17
CPU System Bus Matrix (CPUMX)
18
Matrix (H64MX/H32MX)
19
Special Function Registers (SFR)
20
Special Function Registers Backup (SFRBU)
21
Advanced Interrupt Controller (AIC)
22
Watchdog Timer (WDT)
23
Reset Controller (RSTC)
24
Shutdown Controller (SHDWC)
25
Periodic Interval Timer (PIT)
26
Real-time Clock (RTC)
27
System Controller Write Protection (SYSCWP)
28
Slow Clock Controller (SCKC)
29
Peripheral Touch Controller (PTC)
30
Low Power Asynchronous Receiver (RXLP)
31
Clock Generator
32
Power Management Controller (PMC)
33
Parallel Input/Output Controller (PIO)
34
External Memories
35
DDR-SDRAM Controller (MPDDRC)
36
Static Memory Controller (SMC)
37
DMA Controller (XDMAC)
38
LCD Controller (LCDC)
39
Ethernet MAC (GMAC)
40
USB Device High Speed Port (UDPHS)
41
USB Host High Speed Port (UHPHS)
42
Audio Class D Amplifier (CLASSD)
43
Inter-IC Sound Controller (I2SC)
44
Synchronous Serial Controller (SSC)
45
Two-wire Interface (TWIHS)
46
Flexible Serial Communication Controller (FLEXCOM)
46.1
Description
46.2
Embedded Characteristics
46.3
Block Diagram
46.4
I/O Lines Description
46.5
Product Dependencies
46.6
Register Accesses
46.7
USART Functional Description
46.7.1
Baud Rate Generator
46.7.2
Receiver and Transmitter Control
46.7.3
Synchronous and Asynchronous Modes
46.7.3.1
Transmitter Operations
46.7.3.2
Manchester Encoder
46.7.3.3
Asynchronous Receiver
46.7.3.4
Manchester Decoder
46.7.3.5
Radio Interface: Manchester Encoded USART Application
46.7.3.6
Synchronous Receiver
46.7.3.7
Receiver Operations
46.7.3.8
Parity
46.7.3.9
Multidrop Mode
46.7.3.10
Transmitter Timeguard
46.7.3.11
Receiver Timeout
46.7.3.12
Framing Error
46.7.3.13
Transmit Break
46.7.3.14
Receive Break
46.7.3.15
Hardware Handshaking
46.7.4
ISO7816 Mode
46.7.5
IrDA Mode
46.7.6
RS485 Mode
46.7.7
USART Comparison Function on Received Character
46.7.8
SPI Mode
46.7.9
LIN Mode
46.7.10
Test Modes
46.7.11
USART FIFOs
46.7.12
USART Register Write Protection
46.8
SPI Functional Description
46.9
TWI Functional Description
46.10
Register Summary
47
Universal Asynchronous Receiver Transmitter (UART)
48
Serial Peripheral Interface (SPI)
49
Quad Serial Peripheral Interface (QSPI)
50
Secure Digital MultiMedia Card Controller (SDMMC)
51
Image Sensor Controller (ISC)
52
Controller Area Network (MCAN)
53
Timer Counter (TC)
54
Pulse Density Modulation Interface Controller (PDMIC)
55
Pulse Width Modulation Controller (PWM)
56
Secure Fuse Controller (SFC)
57
Integrity Check Monitor (ICM)
58
Advanced Encryption Standard Bridge (AESB)
59
Advanced Encryption Standard (AES)
60
Secure Hash Algorithm (SHA)
61
Triple Data Encryption Standard (TDES)
62
True Random Number Generator (TRNG)
63
Analog Comparator Controller (ACC)
64
Security Module (SECUMOD)
65
Analog-to-Digital Controller (ADC)
66
Electrical Characteristics
67
Mechanical Characteristics
68
Marking
69
Ordering Information
70
Revision History
Microchip Information
46.7.3 Synchronous and Asynchronous Modes
