19.3.1 DDR Configuration Register
Name: | SFR_DDRCFG |
Offset: | 0x04 |
Reset: | 0x00000001 |
Property: | Read/Write |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
FDQSIEN | FDQIEN | ||||||||
Access | R/W | R/W | |||||||
Reset | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
Access | |||||||||
Reset |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
Access | |||||||||
Reset |
Bit 17 – FDQSIEN Force DDR_DQS Input Buffer Always On
Value | Description |
---|---|
0 | DDR_DQS input buffer controlled by DDR controller. |
1 | DDR_DQS input buffer always on. |
Bit 16 – FDQIEN Force DDR_DQ Input Buffer Always On
Value | Description |
---|---|
0 | DDR_DQ input buffer controlled by DDR controller. |
1 | DDR_DQ input buffer always on. |