39.120 GMAC Interrupt Enable Register Priority Queue x

The following values are valid for all listed bit names of this register:

0: No effect.

1: Enables the corresponding interrupt.

Name: GMAC_IERPQx
Offset: 0x0600 + (x-1)*0x04 [x=1..2]
Reset: 
Property: Write-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
     HRESPROVR   
Access WW 
Reset  
Bit 76543210 
 TCOMPTFCRLEX  RXUBRRCOMP  
Access WWWWW 
Reset  

Bit 11 – HRESP System Bus Error

Bit 10 – ROVR Receive Overrun

Bit 7 – TCOMP Transmit Complete

Bit 6 – TFC Transmit Frame Corruption Due to System Bus Error

Bit 5 – RLEX Retry Limit Exceeded or Late Collision

Bit 2 – RXUBR RX Used Bit Read

Bit 1 – RCOMP Receive Complete