35.7.1 MPDDRC Mode Register
This register can only be written if the WPEN bit is cleared in the MPDDRC Write Protection Mode Register.
| Name: | MPDDRC_MR |
| Offset: | 0x00 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| MRS[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DAI | MODE[2:0] | ||||||||
| Access | R | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bits 15:8 – MRS[7:0] Mode Register Select LPDDR2/LPDDR3
Configure this 8-bit field to program all mode registers included in the low-power DDR2-SDRAM device. This field is unique to the low-power DDR2-SDRAM devices and low-power DDR3-SDRAM devices.
Bit 4 – DAI Device Auto-initialization Status
This field reports when the device auto-initialization is complete. When Backup mode is used, this information is lost after Backup mode exit.
| Value | Name | Description |
|---|---|---|
| 0 | DAI_COMPLETE | DAI complete |
| 1 | DAI_IN_PROGESSS | DAI still in progress |
Bits 2:0 – MODE[2:0] MPDDRC Command Mode
This field defines the command issued by the MPDDRC when the SDRAM device is accessed. This register is used to initialize the SDRAM device and to activate Deep Power-down mode.
| Value | Name | Description |
|---|---|---|
| 0 | NORMAL_CMD | Normal Mode. Any access to the MPDDRC is decoded normally. To activate this mode, the command must be followed by a write to the DDR-SDRAM. |
| 1 | NOP_CMD | The MPDDRC issues a NOP command when the DDR-SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the DDR-SDRAM. |
| 2 | PRCGALL_CMD | The MPDDRC issues the All Banks Pre-charge command when the DDR-SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the SDRAM. |
| 3 | LMR_CMD | The MPDDRC issues a Load Mode Register command when the DDR-SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the DDR-SDRAM. |
| 4 | RFSH_CMD | The MPDDRC issues an Auto-refresh command when the DDR-SDRAM device is accessed regardless of the cycle. Previously, an All Banks Pre-charge command must be issued. To activate this mode, the command must be followed by a write to the DDR-SDRAM. |
| 5 | EXT_LMR_CMD | The MPDDRC issues an Extended Load Mode Register command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the DDR-SDRAM. The write in the DDR-SDRAM must be done in the appropriate bank. |
| 6 | DEEP_CALIB_CMD | Deep Power mode: Access to Deep Power-down mode Calibration command: to calibrate RTT and RON values for the Process Voltage Temperature (PVT) (DDR3-SDRAM device) |
| 7 | LPDDR2_LPDDR3_CMD |
The MPDDRC issues an LPDDR2/LPDDR3 Mode Register command when the device is accessed regardless of the cycle. To activate this mode, the Mode Register command must be followed by a write to the low-power DDR2-SDRAM or to the low-power DDR3-SDRAM. |