31.6.1 Divider and Phase Lock Loop Programming

PLLA is enabled when CKGR_PLLAR.DIVA set to ‘1’.

Whenever the PLLA is re-enabled or one of its parameters is changed, PMC_SR.LOCKA is automatically cleared. The values written in the PLLACOUNT field in the Clock Generator PLLA register (CKGR_PLLAR) are loaded in the PLLA counter. The PLLA counter then decrements at the speed of the Slow clock until it reaches 0. At this time, PMC_SR.LOCKA is set and can trigger an interrupt to the processor. The user has to load the number of Slow clock cycles required to cover the PLLA transient time into CKGR_PLLACOUNT.

The PLLA clock must be divided by 2 by writing PMC_MCKR.PLLADIV2, if the ratio between Processor clock (PCK) and MCK is 3 (MDIV = 3).