6.2 Pinouts

Pinouts are provided in the tables below:

Pin Description (all packages)
Pin Description (SAMA5D23 pins different from those in table ”Pin Description (all packages)” )
Pin Description (SAMA5D28B/C pins different from those in the table ”Pin Description (all packages)” )

I/Os for each peripheral are grouped into IO sets, listed in the column ‘IO Set’ in the pinout tables below. For all peripherals, it is mandatory to use I/Os that belong to the same IO set. The timings are not guaranteed when IOs from different IO sets are mixed.

Table 6-2. Pin Description (all packages)
289-pin BGA	256-pin BGA	196-pin BGA	Power Rail	I/O Type	Primary		Alternate		PIO Peripheral				Reset State (Signal, Dir, PU, PD, HiZ, ST)⁽¹⁾⁽²⁾
289-pin BGA	256-pin BGA	196-pin BGA	Power Rail	I/O Type	Signal	Dir	Signal	Dir	Func	Signal	Dir	IO Set	Reset State (Signal, Dir, PU, PD, HiZ, ST)⁽¹⁾⁽²⁾
U11	R10	–	VDDSDMMC	GPIO_EMMC	PA0	I/O	–	–	A	SDMMC0_CK	I/O	1	PIO, I, PU, ST
									B	QSPI0_SCK	O	1
									F	D0	I/O	2
P10	R9	–	VDDSDMMC	GPIO_EMMC	PA1	I/O	–	–	A	SDMMC0_CMD	I/O	1	PIO, I, PU, ST
									B	QSPI0_CS	O	1
									F	D1	I/O	2
T11	U11	–	VDDSDMMC	GPIO_EMMC	PA2	I/O	–	–	A	SDMMC0_DAT0	I/O	1	PIO, I, PU, ST
									B	QSPI0_IO0	I/O	1
									F	D2	I/O	2
R10	P10	–	VDDSDMMC	GPIO_EMMC	PA3	I/O	–	–	A	SDMMC0_DAT1	I/O	1	PIO, I, PU, ST
									B	QSPI0_IO1	I/O	1
									F	D3	I/O	2
U12	P11	–	VDDSDMMC	GPIO_EMMC	PA4	I/O	–	–	A	SDMMC0_DAT2	I/O	1	PIO, I, PU, ST
									B	QSPI0_IO2	I/O	1
									F	D4	I/O	2
T12	V11	–	VDDSDMMC	GPIO_EMMC	PA5	I/O	–	–	A	SDMMC0_DAT3	I/O	1	PIO, I, PU, ST
									B	QSPI0_IO3	I/O	1
									F	D5	I/O	2
R12	U12	–	VDDSDMMC	GPIO_EMMC	PA6	I/O	–	–	A	SDMMC0_DAT4	I/O	1	PIO, I, PU, ST
									B	QSPI1_SCK	O	1
									D	TIOA5	I/O	1
									E	FLEXCOM2_IO0	I/O	1
									F	D6	I/O	2
T13	V12	–	VDDSDMMC	GPIO_EMMC	PA7	I/O	–	–	A	SDMMC0_DAT5	I/O	1	PIO, I, PU, ST
									B	QSPI1_IO0	I/O	1
									D	TIOB5	I/O	1
									E	FLEXCOM2_IO1	I/O	1
									F	D7	I/O	2
N10	N11	–	VDDSDMMC	GPIO_EMMC	PA8	I/O	–	–	A	SDMMC0_DAT6	I/O	1	PIO, I, PU, ST
									B	QSPI1_IO1	I/O	1
									D	TCLK5	I	1
									E	FLEXCOM2_IO2	I/O	1
									F	NWE/NANDWE	O	2
N11	P12	–	VDDSDMMC	GPIO_EMMC	PA9	I/O	–	–	A	SDMMC0_DAT7	I/O	1	PIO, I, PU, ST
									B	QSPI1_IO2	I/O	1
									D	TIOA4	I/O	1
									E	FLEXCOM2_IO3	O	1
									F	NCS3	O	2
U13	U13	–	VDDSDMMC	GPIO_EMMC	PA10	I/O	–	–	A	SDMMC0_RSTN	O	1	PIO, I, PU, ST
									B	QSPI1_IO3	I/O	1
									D	TIOB4	I/O	1
									E	FLEXCOM2_IO4	O	1
									F	A21/NANDALE	O	2
P15	R14	–	VDDIOP1	GPIO	PA11	I/O	–	–	A	SDMMC0_1V8SEL	O	1	PIO, I, PU, ST
									B	QSPI1_CS	O	1
									D	TCLK4	I	1
									F	A22/NANDCLE	O	2
N15	N13	–	VDDIOP1	GPIO	PA12	I/O	–	–	A	SDMMC0_WP	I	1	PIO, I, PU, ST
									B	IRQ	I	1
									F	NRD/NANDOE	O	2
P16	P14	–	VDDIOP1	GPIO	PA13	I/O	–	–	A	SDMMC0_CD	I	1	PIO, I, PU, ST
									E	FLEXCOM3_IO1	I/O	1
									F	D8	I/O	2
M14	P17	–	VDDIOP1	GPIO_QSPI	PA14	I/O	–	–	A	SPI0_SPCK	I/O	1	PIO, I, PU, ST
									B	TK1	I/O	1
									C	QSPI0_SCK	O	2
									D	I2SC1_MCK	O	2
									E	FLEXCOM3_IO2	I/O	1
									F	D9	I/O	2
N16	R18	–	VDDIOP1	GPIO	PA15	I/O	–	–	A	SPI0_MOSI	I/O	1	PIO, I, PU, ST
									B	TF1	I/O	1
									C	QSPI0_CS	O	2
									D	I2SC1_CK	I/O	2
									E	FLEXCOM3_IO0	I/O	1
									F	D10	I/O	2
M10	N15	–	VDDIOP1	GPIO_IO	PA16	I/O	–	–	A	SPI0_MISO	I/O	1	PIO, I, PU, ST
									B	TD1	O	1
									C	QSPI0_IO0	I/O	2
									D	I2SC1_WS	I/O	2
									E	FLEXCOM3_IO3	I/O	1
									F	D11	I/O	2
N17	P18	–	VDDIOP1	GPIO_IO	PA17	I/O	–	–	A	SPI0_NPCS0	I/O	1	PIO, I, PU, ST
									B	RD1	I	1
									C	QSPI0_IO1	I/O	2
									D	I2SC1_DI0	I	2
									E	FLEXCOM3_IO4	O	1
									F	D12	I/O	2
U14	M9	L9	VDDIOP1	GPIO_IO	PA18	I/O	–	–	A	SPI0_NPCS1	O	1	PIO, I, PU, ST
									B	RK1	I/O	1
									C	QSPI0_IO2	I/O	2
									D	I2SC1_DO0	O	2
									E	SDMMC1_DAT0	I/O	1
									F	D13	I/O	2
T14	V13	N9	VDDIOP1	GPIO_IO	PA19	I/O	–	–	A	SPI0_NPCS2	O	1	PIO, I, PU, ST
									B	RF1	I/O	1
									C	QSPI0_IO3	I/O	2
									D	TIOA0	I/O	1
									E	SDMMC1_DAT1	I/O	1
									F	D14	I/O	2
P12	L9	M9	VDDIOP1	GPIO_IO	PA20	I/O	–	–	A	SPI0_NPCS3	O	1	PIO, I, PU, ST
									D	TIOB0	I/O	1
									E	SDMMC1_DAT2	I/O	1
									F	D15	I/O	2
R13	M10	M10	VDDIOP1	GPIO_IO	PA21	I/O	–	–	A	IRQ	I	2	PIO, I, PU, ST
									B	PCK2	O	3
									D	TCLK0	I	1
									E	SDMMC1_DAT3	I/O	1
									F	NANDRDY	I	2
U15	V14	P9	VDDIOP1	GPIO_QSPI	PA22	I/O	–	–	A	FLEXCOM1_IO2	I/O	1	PIO, I, PU, ST
									B	D0	I/O	1
									C	TCK	I	4
									D	SPI1_SPCK	I/O	2
									E	SDMMC1_CK	I/O	1
									F	QSPI0_SCK	O	3
U16	U14	P10	VDDIOP1	GPIO	PA23	I/O	–	–	A	FLEXCOM1_IO1	I/O	1	PIO, I, PU, ST
									B	D1	I/O	1
									C	TDI	I	4
									D	SPI1_MOSI	I/O	2
									F	QSPI0_CS	O	3
T15	R13	N10	VDDIOP1	GPIO_IO	PA24	I/O	–	–	A	FLEXCOM1_IO0	I/O	1	PIO, I, PU, ST
									B	D2	I/O	1
									C	TDO	O	4
									D	SPI1_MISO	I/O	2
									F	QSPI0_IO0	I/O	3
U17	U15	L10	VDDIOP1	GPIO_IO	PA25	I/O	–	–	A	FLEXCOM1_IO3	O	1	PIO, I, PU, ST
									B	D3	I/O	1
									C	TMS	I	4
									D	SPI1_NPCS0	I/O	2
									F	QSPI0_IO1	I/O	3
P13	L10	P11	VDDIOP1	GPIO_IO	PA26	I/O	–	–	A	FLEXCOM1_IO4	O	1	PIO, I, PU, ST
									B	D4	I/O	1
									C	NTRST	I	4
									D	SPI1_NPCS1	O	2
									F	QSPI0_IO2	I/O	3
T16	V17	P12	VDDIOP1	GPIO_IO	PA27	I/O	–	–	A	TIOA1	I/O	2	PIO, I, PU, ST
									B	D5	I/O	1
									C	SPI0_NPCS2	O	2
									D	SPI1_NPCS2	O	2
									E	SDMMC1_RSTN	O	1
									F	QSPI0_IO3	I/O	3
R16	U16	M11	VDDIOP1	GPIO	PA28	I/O	–	–	A	TIOB1	I/O	2	PIO, I, PU, ST
									B	D6	I/O	1
									C	SPI0_NPCS3	O	2
									D	SPI1_NPCS3	O	2
									E	SDMMC1_CMD	I/O	1
									F	CLASSD_L0	O	1
T17	U17	N11	VDDIOP1	GPIO	PA29	I/O	–	–	A	TCLK1	I	2	PIO, I, PU, ST
									B	D7	I/O	1
									C	SPI0_NPCS1	O	2
									E	SDMMC1_WP	I	1
									F	CLASSD_L1	O	1
R15	V18	N12	VDDIOP1	GPIO	PA30	I/O	–	–	B	NWE/NANDWE	O	1	PIO, I, PU, ST
									C	SPI0_NPCS0	I/O	2
									D	PWMH0	O	1
									E	SDMMC1_CD	I	1
									F	CLASSD_L2	O	1
R17	U18	M12	VDDIOP1	GPIO	PA31	I/O	–	–	B	NCS3	O	1	PIO, I, PU, ST
									C	SPI0_MISO	I/O	2
									D	PWML0	O	1
									F	CLASSD_L3	O	1
J8	G9	A6	VDDIOP0	GPIO	PB0	I/O	–	–	B	A21/NANDALE	O	1	PIO, I, PU, ST
									C	SPI0_MOSI	I/O	2
									D	PWMH1	O	1
A8	A7	A5	VDDIOP0	GPIO	PB1	I/O	–	–	B	A22/NANDCLE	O	1	PIO, I, PU, ST
									C	SPI0_SPCK	I/O	2
									D	PWML1	O	1
									F	CLASSD_R0	O	1
A7	B7	B6	VDDIOP0	GPIO	PB2	I/O	–	–	B	NRD/NANDOE	O	1	PIO, I, PU, ST
									D	PWMFI0	I	1
									F	CLASSD_R1	O	1
A6	B6	B5	VDDIOP0	GPIO	PB3	I/O	–	–	A	URXD4	I	1	PIO, I, PU, ST
									B	D8	I/O	1
									C	IRQ	I	3
									D	PWMEXTRG1	I	1
									F	CLASSD_R2	O	1
B6	A6	A4	VDDIOP0	GPIO	PB4	I/O	–	–	A	UTXD4	O	1	PIO, I, PU, ST
									B	D9	I/O	1
									C	FIQ	I	4
									F	CLASSD_R3	O	1
B7	D7	D6	VDDIOP0	GPIO_QSPI	PB5	I/O	–	–	A	TCLK2	I	1	PIO, I, PU, ST
									B	D10	I/O	1
									C	PWMH2	O	1
									D	QSPI1_SCK	O	2
									F	GTSUCOMP	O	3
C7	B5	A3	VDDIOP0	GPIO	PB6	I/O	–	–	A	TIOA2	I/O	1	PIO, I, PU, ST
									B	D11	I/O	1
									C	PWML2	O	1
									D	QSPI1_CS	O	2
									F	GTXER	O	3
C6	A5	B4	VDDIOP0	GPIO_IO	PB7	I/O	–	–	A	TIOB2	I/O	1	PIO, I, PU, ST
									B	D12	I/O	1
									C	PWMH3	O	1
									D	QSPI1_IO0	I/O	2
									F	GRXCK	I	3
A5	E7	A2	VDDIOP0	GPIO_IO	PB8	I/O	–	–	A	TCLK3	I	1	PIO, I, PU, ST
									B	D13	I/O	1
									C	PWML3	O	1
									D	QSPI1_IO1	I/O	2
									F	GCRS	I	3
A4	F6	B3	VDDIOP0	GPIO_IO	PB9	I/O	–	–	A	TIOA3	I/O	1	PIO, I, PU, ST
									B	D14	I/O	1
									C	PWMFI1	I	1
									D	QSPI1_IO2	I/O	2
									F	GCOL	I	3
H8	D6	A1	VDDIOP0	GPIO_IO	PB10	I/O	–	–	A	TIOB3	I/O	1	PIO, I, PU, ST
									B	D15	I/O	1
									C	PWMEXTRG2	I	1
									D	QSPI1_IO3	I/O	2
									F	GRX2	I	3
B5	A4	B1	VDDIOP0	GPIO	PB11	I/O	–	–	A	LCDDAT0	O	1	PIO, I, PU, ST
									B	A0/NBS0	O	1
									C	URXD3	I	3
									D	PDMIC_DAT		2
									F	GRX3	I	3
D6	B3	B2	VDDIOP0	GPIO	PB12	I/O	–	–	A	LCDDAT1	O	1	PIO, I, PU, ST
									B	A1	O	1
									C	UTXD3	O	3
									D	PDMIC_CLK		2
									F	GTX2	O	3
B4	A3	C1	VDDIOP0	GPIO	PB13	I/O	–	–	A	LCDDAT2	O	1	PIO, I, PU, ST
									B	A2	O	1
									C	PCK1	O	3
									F	GTX3	O	3
C5	B4	D5	VDDIOP0	GPIO_QSPI	PB14	I/O	–	–	A	LCDDAT3	O	1	PIO, I, PU, ST
									B	A3	O	1
									C	TK1	I/O	2
									D	I2SC1_MCK	O	1
									E	QSPI1_SCK	O	3
									F	GTXCK	I/O	3
H7	G8	E5	VDDIOP0	GPIO	PB15	I/O	–	–	A	LCDDAT4	O	1	PIO, I, PU, ST
									B	A4	O	1
									C	TF1	I/O	2
									D	I2SC1_CK	I/O	1
									E	QSPI1_CS	O	3
									F	GTXEN	O	3
D5	E5	C5	VDDIOP0	GPIO_IO	PB16	I/O	–	–	A	LCDDAT5	O	1	PIO, I, PU, ST
									B	A5	O	1
									C	TD1	O	2
									D	I2SC1_WS	I/O	1
									E	QSPI1_IO0	I/O	3
									F	GRXDV	I	3
C4	G7	C2	VDDIOP0	GPIO_IO	PB17	I/O	–	–	A	LCDDAT6	O	1	PIO, I, PU, ST
									B	A6	O	1
									C	RD1	I	2
									D	I2SC1_DI0	I	1
									E	QSPI1_IO1	I/O	3
									F	GRXER	I	3
A3	A2	D4	VDDIOP0	GPIO_IO	PB18	I/O	–	–	A	LCDDAT7	O	1	PIO, I, PU, ST
									B	A7	O	1
									C	RK1	I/O	2
									D	I2SC1_DO0	O	1
									E	QSPI1_IO2	I/O	3
									F	GRX0	I	3
D4	H7	C4	VDDIOP0	GPIO_IO	PB19	I/O	–	–	A	LCDDAT8	O	1	PIO, I, PU, ST
									B	A8	O	1
									C	RF1	I/O	2
									D	TIOA3	I/O	2
									E	QSPI1_IO3	I/O	3
									F	GRX1	I	3
B3	A1	C3	VDDIOP0	GPIO	PB20	I/O	–	–	A	LCDDAT9	O	1	PIO, I, PU, ST
									B	A9	O	1
									C	TK0	I/O	1
									D	TIOB3	I/O	2
									E	PCK1	O	4
									F	GTX0	O	3
A2	D2	D1	VDDIOP0	GPIO	PB21	I/O	–	–	A	LCDDAT10	O	1	PIO, I, PU, ST
									B	A10	O	1
									C	TF0	I/O	1
									D	TCLK3	I	2
									E	FLEXCOM3_IO2	I/O	3
									F	GTX1	O	3
C3	G5	D2	VDDIOP0	GPIO	PB22	I/O	–	–	A	LCDDAT11	O	1	PIO, I, PU, ST
									B	A11	O	1
									C	TD0	O	1
									D	TIOA2	I/O	2
									E	FLEXCOM3_IO1	I/O	3
									F	GMDC	O	3
A1	C2	E1	VDDIOP0	GPIO	PB23	I/O	–	–	A	LCDDAT12	O	1	PIO, I, PU, ST
									B	A12	O	1
									C	RD0	I	1
									D	TIOB2	I/O	2
									E	FLEXCOM3_IO0	I/O	3
									F	GMDIO	I/O	3
E5	F4	D3	VDDIOP0	GPIO	PB24	I/O	–	–	A	LCDDAT13	O	1	PIO, I, PU, ST
									B	A13	O	1
									C	RK0	I/O	1
									D	TCLK2	I	2
									E	FLEXCOM3_IO3	I/O	3
									F	ISC_D10	I	3
B2	C1	E3	VDDIOP0	GPIO	PB25	I/O	–	–	A	LCDDAT14	O	1	PIO, I, PU, ST
									B	A14	O	1
									C	RF0	I/O	1
									E	FLEXCOM3_IO4	O	3
									F	ISC_D11	I	3
E4	E4	E2	VDDIOP0	GPIO	PB26	I/O	–	–	A	LCDDAT15	O	1	PIO, I, PU, ST
									B	A15	O	1
									C	URXD0	I	1
									D	PDMIC_DAT		1
									F	ISC_D0	I	3
B1	F1	E6	VDDIOP0	GPIO	PB27	I/O	–	–	A	LCDDAT16	O	1	PIO, I, PU, ST
									B	A16	O	1
									C	UTXD0	O	1
									D	PDMIC_CLK		1
									F	ISC_D1	I	3
C2	D1	F1	VDDIOP0	GPIO	PB28	I/O	–	–	A	LCDDAT17	O	1	PIO, I, PU, ST
									B	A17	O	1
									C	FLEXCOM0_IO0	I/O	1
									D	TIOA5	I/O	2
									F	ISC_D2	I	3
D3	F2	F6	VDDIOP0	GPIO	PB29	I/O	–	–	A	LCDDAT18	O	1	PIO, I, PU, ST
									B	A18	O	1
									C	FLEXCOM0_IO1	I/O	1
									D	TIOB5	I/O	2
									F	ISC_D3	I	3
D2	E2	F2	VDDIOP0	GPIO	PB30	I/O	–	–	A	LCDDAT19	O	1	PIO, I, PU, ST
									B	A19	O	1
									C	FLEXCOM0_IO2	I/O	1
									D	TCLK5	I	2
									F	ISC_D4	I	3
C1	E1	F7	VDDIOP0	GPIO	PB31	I/O	–	–	A	LCDDAT20	O	1	PIO, I, PU, ST
									B	A20	O	1
									C	FLEXCOM0_IO3	O	1
									D	TWD0	I/O	1
									F	ISC_D5	I	3
P17	R15	M13	VDDIOP1	GPIO	PC0	I/O	–	–	A	LCDDAT21	O	1	PIO, I, PU, ST
									B	A23	O	1
									C	FLEXCOM0_IO4	O	1
									D	TWCK0	I/O	1
									F	ISC_D6	I	3
N12	M11	P13	VDDIOP1	GPIO	PC1	I/O	–	–	A	LCDDAT22	O	1	PIO, I, PU, ST
									B	A24	O	1
									C	CANTX0	O	1
									D	SPI1_SPCK	I/O	1
									E	I2SC0_CK	I/O	1
									F	ISC_D7	I	3
N14	P15	N13	VDDIOP1	GPIO	PC2	I/O	–	–	A	LCDDAT23	O	1	PIO, I, PU, ST
									B	A25	O	1
									C	CANRX0	I	1
									D	SPI1_MOSI	I/O	1
									E	I2SC0_MCK	O	1
									F	ISC_D8	I	3
M15	K9	K10	VDDIOP1	GPIO	PC3	I/O	–	–	A	LCDPWM	O	1	PIO, I, PU, ST
									B	NWAIT	I	1
									C	TIOA1	I/O	1
									D	SPI1_MISO	I/O	1
									E	I2SC0_WS	I/O	1
									F	ISC_D9	I	3
M11	K10	P14	VDDIOP1	GPIO	PC4	I/O	–	–	A	LCDDISP	O	1	PIO, I, PU, ST
									B	NWR1/NBS1	O	1
									C	TIOB1	I/O	1
									D	SPI1_NPCS0	I/O	1
									E	I2SC0_DI0	I	1
									F	ISC_PCK	I	3
L10	L11	J8	VDDIOP1	GPIO	PC5	I/O	–	–	A	LCDVSYNC	O	1	PIO, I, PU, ST
									B	NCS0	O	1
									C	TCLK1	I	1
									D	SPI1_NPCS1	O	1
									E	I2SC0_DO0	O	1
									F	ISC_VSYNC	I	3
K10	L12	N14	VDDIOP1	GPIO	PC6	I/O	–	–	A	LCDHSYNC	O	1	PIO, I, PU, ST
									B	NCS1	O	1
									C	TWD1	I/O	1
									D	SPI1_NPCS2	O	1
									F	ISC_HSYNC	I	3
M16	M12	M14	VDDIOP1	GPIO_CLK	PC7	I/O	–	–	A	LCDPCK	O	1	PIO, I, PU, ST
									B	NCS2	O	1
									C	TWCK1	I/O	1
									D	SPI1_NPCS3	O	1
									E	URXD1	I	2
									F	ISC_MCK	O	3
J10	K11	J9	VDDIOP1	GPIO	PC8	I/O	–	–	A	LCDDEN	O	1	PIO, I, PU, ST
									B	NANDRDY	I	1
									C	FIQ	I	1
									D	PCK0	O	3
									E	UTXD1	O	2
									F	ISC_FIELD	I	3
D1	–	–	VDDISC	GPIO	PC9	I/O	–	–	A	FIQ	I	3	PIO, I, PU, ST
									B	GTSUCOMP	O	1
									C	ISC_D0	I	1
									D	TIOA4	I/O	2
E3	–	–	VDDISC	GPIO	PC10	I/O	–	–	A	LCDDAT2	O	2	PIO, I, PU, ST
									B	GTXCK	I/O	1
									C	ISC_D1	I	1
									D	TIOB4	I/O	2
									E	CANTX0	O	2
E2	–	–	VDDISC	GPIO	PC11	I/O	–	–	A	LCDDAT3	O	2	PIO, I, PU, ST
									B	GTXEN	O	1
									C	ISC_D2	I	1
									D	TCLK4	I	2
									E	CANRX0	I	2
									F	A0/NBS0	O	2
E1	–	–	VDDISC	GPIO	PC12	I/O	–	–	A	LCDDAT4	O	2	PIO, I, PU, ST
									B	GRXDV	I	1
									C	ISC_D3	I	1
									D	URXD3	I	1
									E	TK0	I/O	2
									F	A1	O	2
F3	–	–	VDDISC	GPIO	PC13	I/O	–	–	A	LCDDAT5	O	2	PIO, I, PU, ST
									B	GRXER	I	1
									C	ISC_D4	I	1
									D	UTXD3	O	1
									E	TF0	I/O	2
									F	A2	O	2
F5	–	–	VDDISC	GPIO	PC14	I/O	–	–	A	LCDDAT6	O	2	PIO, I, PU, ST
									B	GRX0	I	1
									C	ISC_D5	I	1
									E	TD0	O	2
									F	A3	O	2
F2	–	–	VDDISC	GPIO	PC15	I/O	–	–	A	LCDDAT7	O	2	PIO, I, PU, ST
									B	GRX1	I	1
									C	ISC_D6	I	1
									E	RD0	I	2
									F	A4	O	2
G6	–	–	VDDISC	GPIO	PC16	I/O	–	–	A	LCDDAT10	O	2	PIO, I, PU, ST
									B	GTX0	O	1
									C	ISC_D7	I	1
									E	RK0	I/O	2
									F	A5	O	2
F1	–	–	VDDISC	GPIO	PC17	I/O	–	–	A	LCDDAT11	O	2	PIO, I, PU, ST
									B	GTX1	O	1
									C	ISC_D8	I	1
									E	RF0	I/O	2
									F	A6	O	2
H6	–	–	VDDISC	GPIO	PC18	I/O	–	–	A	LCDDAT12	O	2	PIO, I, PU, ST
									B	GMDC	O	1
									C	ISC_D9	I	1
									E	FLEXCOM3_IO2	I/O	2
									F	A7	O	2
G2	–	–	VDDISC	GPIO	PC19	I/O	–	–	A	LCDDAT13	O	2	PIO, I, PU, ST
									B	GMDIO	I/O	1
									C	ISC_D10	I	1
									E	FLEXCOM3_IO1	I/O	2
									F	A8	O	2
G3	–	–	VDDISC	GPIO	PC20	I/O	–	–	A	LCDDAT14	O	2	PIO, I, PU, ST
									B	GRXCK	I	1
									C	ISC_D11	I	1
									E	FLEXCOM3_IO0	I/O	2
									F	A9	O	2
G1	–	–	VDDISC	GPIO	PC21	I/O	–	–	A	LCDDAT15	O	2	PIO, I, PU, ST
									B	GTXER	O	1
									C	ISC_PCK	I	1
									E	FLEXCOM3_IO3	I/O	2
									F	A10	O	2
H2	–	–	VDDISC	GPIO	PC22	I/O	–	–	A	LCDDAT18	O	2	PIO, I, PU, ST
									B	GCRS	I	1
									C	ISC_VSYNC	I	1
									E	FLEXCOM3_IO4	O	2
									F	A11	O	2
G5	–	–	VDDISC	GPIO	PC23	I/O	–	–	A	LCDDAT19	O	2	PIO, I, PU, ST
									B	GCOL	I	1
									C	ISC_HSYNC	I	1
									F	A12	O	2
H1	–	–	VDDISC	GPIO_CLK	PC24	I/O	–	–	A	LCDDAT20	O	2	PIO, I, PU, ST
									B	GRX2	I	1
									C	ISC_MCK	O	1
									F	A13	O	2
H5	–	–	VDDISC	GPIO	PC25	I/O	–	–	A	LCDDAT21	O	2	PIO, I, PU, ST
									B	GRX3	I	1
									C	ISC_FIELD	I	1
									F	A14	O	2
J9	–	–	VDDIOP2	GPIO	PC26	I/O	–	–	A	LCDDAT22	O	2	PIO, I, PU, ST
									B	GTX2	O	1
									D	CANTX1	O	1
									F	A15	O	2
H9	–	–	VDDIOP2	GPIO	PC27	I/O	–	–	A	LCDDAT23	O	2	PIO, I, PU, ST
									B	GTX3	O	1
									C	PCK1	O	2
									D	CANRX1	I	1
									E	TWD0	I/O	2
									F	A16	O	2
E8	–	–	VDDIOP2	GPIO	PC28	I/O	–	–	A	LCDPWM	O	2	PIO, I, PU, ST
									B	FLEXCOM4_IO0	I/O	1
									C	PCK2	O	1
									E	TWCK0	I/O	2
									F	A17	O	2
G8	–	–	VDDIOP2	GPIO	PC29	I/O	–	–	A	LCDDISP	O	2	PIO, I, PU, ST
									B	FLEXCOM4_IO1	I/O	1
									F	A18	O	2
F8	–	–	VDDIOP2	GPIO	PC30	I/O	–	–	A	LCDVSYNC	O	2	PIO, I, PU, ST
									B	FLEXCOM4_IO2	I/O	1
									F	A19	O	2
D8	–	–	VDDIOP2	GPIO	PC31	I/O	–	–	A	LCDHSYNC	O	2	PIO, I, PU, ST
									B	FLEXCOM4_IO3	O	1
									C	URXD3	I	2
									F	A20	O	2
G10	E9	–	VDDIOP2	GPIO_CLK	PD0	I/O	–	–	A	LCDPCK	O	2	PIO, I, PU, ST
									B	FLEXCOM4_IO4	O	1
									C	UTXD3	O	2
									D	GTSUCOMP	O	2
									F	A23	O	2
E10	F8	–	VDDIOP2	GPIO	PD1	I/O	–	–	A	LCDDEN	O	2	PIO, I, PU, ST
									D	GRXCK	I	2
									F	A24	O	2
G9	F9	–	VDDIOP2	GPIO_CLK	PD2	I/O	–	–	A	URXD1	I	1	PIO, I, PU, ST
									D	GTXER	O	2
									E	ISC_MCK	O	2
									F	A25	O	2
K1	J4	–	VDDANA	GPIO_AD	PD3	I/O	PTC_X0	–	A	UTXD1	O	1	PIO, I, PU, ST
									B	FIQ	I	2
									D	GCRS	I	2
									E	ISC_D11	I	2
									F	NWAIT	I	2
J6	H6	–	VDDANA	GPIO_AD	PD4	I/O	PTC_X1	–	A	TWD1	I/O	2	PIO, I, PU, ST
									B	URXD2	I	1
									D	GCOL	I	2
									E	ISC_D10	I	2
									F	NCS0	O	2
J4	H1	–	VDDANA	GPIO_AD	PD5	I/O	PTC_X2	–	A	TWCK1	I/O	2	PIO, I, PU, ST
									B	UTXD2	O	1
									D	GRX2	I	2
									E	ISC_D9	I	2
									F	NCS1	O	2
J2	G4	–	VDDANA	GPIO_AD	PD6	I/O	PTC_X3	–	A	TCK	I	2	PIO, I, PU, ST
									B	PCK1	O	1
									D	GRX3	I	2
									E	ISC_D8	I	2
									F	NCS2	O	2
J7	H5	F5	VDDANA	GPIO_AD	PD7	I/O	PTC_X4	–	A	TDI	I	2	PIO, I, PU, ST
									C	UTMI_RXVAL	O	1
									D	GTX2	O	2
									E	ISC_D0	I	2
									F	NWR1/NBS1	O	2
J1	G1	F3	VDDANA	GPIO_AD	PD8	I/O	PTC_X5	–	A	TDO	O	2	PIO, I, PU, ST
									C	UTMI_RXERR	O	1
									D	GTX3	O	2
									E	ISC_D1	I	2
									F	NANDRDY	I	2
K9	H4	G5	VDDANA	GPIO_AD	PD9	I/O	PTC_X6	–	A	TMS	I	2	PIO, I, PU, ST
									C	UTMI_RXACT	O	1
									D	GTXCK	I/O	2
									E	ISC_D2	I	2
J3	G2	G4	VDDANA	GPIO_AD	PD10	I/O	PTC_X7	–	A	NTRST	I	2	PIO, I, PU, ST
									C	UTMI_HDIS	O	1
									D	GTXEN	O	2
									E	ISC_D3	I	2
M1	H2	H1	VDDANA	GPIO_AD	PD11	I/O	PTC_Y0	–	A	TIOA1	I/O	3	PIO, I, PU, ST
									B	PCK2	O	2
									C	UTMI_LS0	O	1
									D	GRXDV	I	2
									E	ISC_D4	I	2
									F	ISC_MCK	O	4
K8	K5	H6	VDDANA	GPIO_AD	PD12	I/O	PTC_Y1	–	A	TIOB1	I/O	3	PIO, I, PU, ST
									B	FLEXCOM4_IO0	I/O	2
									C	UTMI_LS1	O	1
									D	GRXER	I	2
									E	ISC_D5	I	2
									F	ISC_D4	I	4
L2	J5	H3	VDDANA	GPIO_AD	PD13	I/O	PTC_Y2	–	A	TCLK1	I	3	PIO, I, PU, ST
									B	FLEXCOM4_IO1	I/O	2
									C	UTMI_CDRCPSEL0	I	1
									D	GRX0	I	2
									E	ISC_D6	I	2
									F	ISC_D5	I	4
K4	K6	G6	VDDANA	GPIO_AD	PD14	I/O	PTC_Y3	–	A	TCK⁽⁴⁾	I	1	A, PU, ST
									B	FLEXCOM4_IO2	I/O	2
									C	UTMI_CDRCPSEL1	I	1
									D	GRX1	I	2
									E	ISC_D7	I	2
									F	ISC_D6	I	4
K7	K4	H5	VDDANA	GPIO_AD	PD15	I/O	PTC_Y4	–	A	TDI⁽⁴⁾	I	1	PIO, I, PU, ST
									B	FLEXCOM4_IO3	O	2
									C	UTMI_CDRCPDIVEN	I	1
									D	GTX0	O	2
									E	ISC_PCK	I	2
									F	ISC_D7	I	4
L1	K1	G1	VDDANA	GPIO_AD	PD16	I/O	PTC_Y5	–	A	TDO⁽⁴⁾	O	1	PIO, I, PU, ST
									B	FLEXCOM4_IO4	O	2
									C	UTMI_CDRBISTEN	I	1
									D	GTX1	O	2
									E	ISC_VSYNC	I	2
									F	ISC_D8	I	4
K2	K2	G2	VDDANA	GPIO_AD	PD17	I/O	PTC_Y6	–	A	TMS⁽⁴⁾	I	1	A, PU, ST
									C	UTMI_CDRCPSELDIV	O	1
									D	GMDC	O	2
									E	ISC_HSYNC	I	2
									F	ISC_D9	I	4
J5	L5	G3	VDDANA	GPIO_AD	PD18	I/O	PTC_Y7	–	A	NTRST⁽⁴⁾	I	1	PIO, I, PU, ST
									D	GMDIO	I/O	2
									E	ISC_FIELD	I	2
									F	ISC_D10	I	4
K6	L4	H4	VDDANA	GPIO_AD	PD19	I/O	AD0	–	A	PCK0	O	1	PIO, I, PU, ST
									B	TWD1	I/O	3
									C	URXD2	I	3
									E	I2SC0_CK	I/O	2
									F	ISC_D11	I	4
M2	M1	J1	VDDANA	GPIO_AD	PD20	I/O	AD1	–	A	TIOA2	I/O	3	PIO, I, PU, ST
									B	TWCK1	I/O	3
									C	UTXD2	O	3
									E	I2SC0_MCK	O	2
									F	ISC_PCK	I	4
N1	M2	K1	VDDANA	GPIO_AD	PD21	I/O	AD2	–	A	TIOB2	I/O	3	PIO, I, PU, ST
									B	TWD0	I/O	4
									C	FLEXCOM4_IO0	I/O	3
									E	I2SC0_WS	I/O	2
									F	ISC_VSYNC	I	4
L4	M4	J3	VDDANA	GPIO_AD	PD22	I/O	AD3	–	A	TCLK2	I	3	PIO, I, PU, ST
									B	TWCK0	I/O	4
									C	FLEXCOM4_IO1	I/O	3
									E	I2SC0_DI0	I	2
									F	ISC_HSYNC	I	4
M3	P1	K2	VDDANA	GPIO_AD	PD23	I/O	AD4	–	A	URXD2	I	2	PIO, I, PU, ST
									C	FLEXCOM4_IO2	I/O	3
									E	I2SC0_DO0	O	2
									F	ISC_FIELD	I	4
L7	L6	–	VDDANA	GPIO_AD	PD24	I/O	AD5	–	A	UTXD2	O	2	PIO, I, PU, ST
L7	L6	–	VDDANA	GPIO_AD	PD24	I/O	AD5	–	C	FLEXCOM4_IO3	O	3	PIO, I, PU, ST
L6	M5	–	VDDANA	GPIO_AD	PD25	I/O	AD6	–	A	SPI1_SPCK	I/O	3	PIO, I, PU, ST
L6	M5	–	VDDANA	GPIO_AD	PD25	I/O	AD6	–	C	FLEXCOM4_IO4	O	3	PIO, I, PU, ST
N2	N1	–	VDDANA	GPIO_AD	PD26	I/O	AD7	–	A	SPI1_MOSI	I/O	3	PIO, I, PU, ST
N2	N1	–	VDDANA	GPIO_AD	PD26	I/O	AD7	–	C	FLEXCOM2_IO0	I/O	2	PIO, I, PU, ST
L8	N2	–	VDDANA	GPIO_AD	PD27	I/O	AD8	–	A	SPI1_MISO	I/O	3	PIO, I, PU, ST
									B	TCK	I	3
									C	FLEXCOM2_IO1	I/O	2
M4	P2	–	VDDANA	GPIO_AD	PD28	I/O	AD9	–	A	SPI1_NPCS0	I/O	3	PIO, I, PU, ST
									B	TDI	I	3
									C	FLEXCOM2_IO2	I/O	2
N3	R1	–	VDDANA	GPIO_AD	PD29	I/O	AD10	–	A	SPI1_NPCS1	O	3	PIO, I, PU, ST
									B	TDO	O	3
									C	FLEXCOM2_IO3	O	2
									D	TIOA3	I/O	3
									E	TWD0	I/O	3
L9	N4	–	VDDANA	GPIO_AD	PD30	I/O	AD11	–	A	SPI1_NPCS2	O	3	PIO, I, PU, ST
									B	TMS	I	3
									C	FLEXCOM2_IO4	O	2
									D	TIOB3	I/O	3
									E	TWCK0	I/O	3
M7	T1	–	VDDANA	GPIO	PD31	I/O	–	–	A	ADTRG	I	1	PIO, I, PU, ST
									B	NTRST	I	3
									C	IRQ	I	4
									D	TCLK3	I	3
									E	PCK0	O	2
L5	L1	K3	VDDANA	power	VDDANA	I	–	–	–	–	–	–	–
K5	L2	K4	GNDANA	ground	GNDANA	I	–	–	–	–	–	–	–
M6	P5	L2	VDDANA	–	ADVREF	I	–	–	–	–	–	–	–
K3	J1	H2	VDDANA	power	VDDANA	I	–	–	–	–	–	–	–
L3	J2	J2	GNDANA	ground	GNDANA	I	–	–	–	–	–	–	–
H16, D16	J17, D12	H12, C12	VDDIODDR	DDR	DDR_VREF	I	–	–	–	–	–	–	–
B12	B12	B7	VDDIODDR	DDR	DDR_D0	I/O	–	–	–	–	–	–	–
A12	B13	A7	VDDIODDR	DDR	DDR_D1	I/O	–	–	–	–	–	–	–
C12	D13	C8	VDDIODDR	DDR	DDR_D2	I/O	–	–	–	–	–	–	–
A13	A13	B9	VDDIODDR	DDR	DDR_D3	I/O	–	–	–	–	–	–	–
A14	A15	A9	VDDIODDR	DDR	DDR_D4	I/O	–	–	–	–	–	–	–
C13	D14	C9	VDDIODDR	DDR	DDR_D5	I/O	–	–	–	–	–	–	–
A15	B15	A10	VDDIODDR	DDR	DDR_D6	I/O	–	–	–	–	–	–	–
B15	B16	B10	VDDIODDR	DDR	DDR_D7	I/O	–	–	–	–	–	–	–
G17	G18	H13	VDDIODDR	DDR	DDR_D8	I/O	–	–	–	–	–	–	–
G16	K17	H14	VDDIODDR	DDR	DDR_D9	I/O	–	–	–	–	–	–	–
H17	J13	J13	VDDIODDR	DDR	DDR_D10	I/O	–	–	–	–	–	–	–
K17	H15	J14	VDDIODDR	DDR	DDR_D11	I/O	–	–	–	–	–	–	–
K16	J15	L13	VDDIODDR	DDR	DDR_D12	I/O	–	–	–	–	–	–	–
J13	J14	L14	VDDIODDR	DDR	DDR_D13	I/O	–	–	–	–	–	–	–
K14	K13	J12	VDDIODDR	DDR	DDR_D14	I/O	–	–	–	–	–	–	–
K15	K18	K12	VDDIODDR	DDR	DDR_D15	I/O	–	–	–	–	–	–	–
B8	A8	–	VDDIODDR	DDR	DDR_D16	I/O	–	–	–	–	–	–	–
B9	B9	–	VDDIODDR	DDR	DDR_D17	I/O	–	–	–	–	–	–	–
C9	D9	–	VDDIODDR	DDR	DDR_D18	I/O	–	–	–	–	–	–	–
A9	A9	–	VDDIODDR	DDR	DDR_D19	I/O	–	–	–	–	–	–	–
A10	B11	–	VDDIODDR	DDR	DDR_D20	I/O	–	–	–	–	–	–	–
D10	D10	–	VDDIODDR	DDR	DDR_D21	I/O	–	–	–	–	–	–	–
B11	A11	–	VDDIODDR	DDR	DDR_D22	I/O	–	–	–	–	–	–	–
A11	A12	–	VDDIODDR	DDR	DDR_D23	I/O	–	–	–	–	–	–	–
J12	L18	–	VDDIODDR	DDR	DDR_D24	I/O	–	–	–	–	–	–	–
H10	K15	–	VDDIODDR	DDR	DDR_D25	I/O	–	–	–	–	–	–	–
J11	K14	–	VDDIODDR	DDR	DDR_D26	I/O	–	–	–	–	–	–	–
K11	M18	–	VDDIODDR	DDR	DDR_D27	I/O	–	–	–	–	–	–	–
L13	N17	–	VDDIODDR	DDR	DDR_D28	I/O	–	–	–	–	–	–	–
L11	M14	–	VDDIODDR	DDR	DDR_D29	I/O	–	–	–	–	–	–	–
L12	M15	–	VDDIODDR	DDR	DDR_D30	I/O	–	–	–	–	–	–	–
M17	N18	–	VDDIODDR	DDR	DDR_D31	I/O	–	–	–	–	–	–	–
F12	D17	E11	VDDIODDR	DDR	DDR_A0	O	–	–	–	–	–	–	–
C17	A17	C11	VDDIODDR	DDR	DDR_A1	O	–	–	–	–	–	–	–
B17	A18	B12	VDDIODDR	DDR	DDR_A2	O	–	–	–	–	–	–	–
B16	F15	A12	VDDIODDR	DDR	DDR_A3	O	–	–	–	–	–	–	–
C16	G12	D11	VDDIODDR	DDR	DDR_A4	O	–	–	–	–	–	–	–
G14	H12	D14	VDDIODDR	DDR	DDR_A5	O	–	–	–	–	–	–	–
F14	F13	B14	VDDIODDR	DDR	DDR_A6	O	–	–	–	–	–	–	–
F11	H10	D9	VDDIODDR	DDR	DDR_A7	O	–	–	–	–	–	–	–
C14	A16	C10	VDDIODDR	DDR	DDR_A8	O	–	–	–	–	–	–	–
D13	E12	D10	VDDIODDR	DDR	DDR_A9	O	–	–	–	–	–	–	–
C15	H11	F9	VDDIODDR	DDR	DDR_A10	O	–	–	–	–	–	–	–
A16	J10	A11	VDDIODDR	DDR	DDR_A11	O	–	–	–	–	–	–	–
A17	D15	B11	VDDIODDR	DDR	DDR_A12	O	–	–	–	–	–	–	–
G11	J11	E13	VDDIODDR	DDR	DDR_A13	O	–	–	–	–	–	–	–
E17	C18	A13	VDDIODDR	DDR	DDR_CLK	O	–	–	–	–	–	–	–
D17	C17	B13	VDDIODDR	DDR	DDR_CLKN	O	–	–	–	–	–	–	–
F16	F18	E14	VDDIODDR	DDR	DDR_CKE	O	–	–	–	–	–	–	–
E16	F17	D13	VDDIODDR	DDR	DDR_RESETN	O	–	–	–	–	–	–	–
G13	J12	F11	VDDIODDR	DDR	DDR_CS	O	–	–	–	–	–	–	–
F15	D18	A14	VDDIODDR	DDR	DDR_WE	O	–	–	–	–	–	–	–
F13	E18	C14	VDDIODDR	DDR	DDR_RAS	O	–	–	–	–	–	–	–
G12	E17	C13	VDDIODDR	DDR	DDR_CAS	O	–	–	–	–	–	–	–
C11	D11	D8	VDDIODDR	DDR	DDR_DQM0	O	–	–	–	–	–	–	–
G15	H14	G14	VDDIODDR	DDR	DDR_DQM1	O	–	–	–	–	–	–	–
C8	B8	–	VDDIODDR	DDR	DDR_DQM2	O	–	–	–	–	–	–	–
H11	L13	–	VDDIODDR	DDR	DDR_DQM3	O	–	–	–	–	–	–	–
B13	A14	B8	VDDIODDR	DDR	DDR_DQS0	O	–	–	–	–	–	–	–
J17	H18	K14	VDDIODDR	DDR	DDR_DQS1	O	–	–	–	–	–	–	–
C10	A10	–	VDDIODDR	DDR	DDR_DQS2	O	–	–	–	–	–	–	–
L17	M17	–	VDDIODDR	DDR	DDR_DQS3	O	–	–	–	–	–	–	–
B14	B14	A8	VDDIODDR	DDR	DDR_DQSN0	O	–	–	–	–	–	–	–
J16	J18	K13	VDDIODDR	DDR	DDR_DQSN1	O	–	–	–	–	–	–	–
B10	B10	–	VDDIODDR	DDR	DDR_DQSN2	O	–	–	–	–	–	–	–
L16	L17	–	VDDIODDR	DDR	DDR_DQSN3	O	–	–	–	–	–	–	–
H12	H13	F13	VDDIODDR	DDR	DDR_BA0	O	–	–	–	–	–	–	–
H13	K12	G13	VDDIODDR	DDR	DDR_BA1	O	–	–	–	–	–	–	–
F17	H17	F14	VDDIODDR	DDR	DDR_BA2	O	–	–	–	–	–	–	–
E13	G17	F10	VDDIODDR	DDR	DDR_CAL	I	–	–	–	–	–	–	–
L15, J15, H15, E15, D15, D12, D11	B17, E11, E14, F10, G11, G15, L14	C6, E10, E12, G10, G12, H11, J10	VDDIODDR	power	VDDIODDR	I	–	–	–	–	–	–	–
L14, J14, H14, E14, D14, E12, E11	B18, E10, E15, F11, G10, G14, L15	C7, D12, E9, F12, G11, H10, J11	GNDIODDR	ground	GNDIODDR	I	–	–	–	–	–	–	–
H3, N5, N9, K13, D9, D7	H8, J6, J9, K8, L8	E8, G8, H8, H9, J5	VDDCORE	power	VDDCORE	I	–	–	–	–	–	–	–
H4, M5, M9, K12, E9, E7	H9, J7, J8, K7, L7	F8, G7, G9, H7, J4	GNDCORE	ground	GNDCORE	I	–	–	–	–	–	–	–
E6, F7	B1, D5	D7, F4	VDDIOP0	power	VDDIOP0	I	–	–	–	–	–	–	–
F6, G7	B2, D4	E4, E7	GNDIOP0	ground	GNDIOP0	I	–	–	–	–	–	–	–
R14, N13	T18, V16	K8, L11	VDDIOP1	power	VDDIOP1	I	–	–	–	–	–	–	–
M13, P14	T17, V15	K9, L12	GNDIOP1	ground	GNDIOP1	I	–	–	–	–	–	–	–
F10	D8	–	VDDIOP2	power	VDDIOP2	I	–	–	–	–	–	–	–
F9	E8	–	GNDIOP2	ground	GNDIOP2	I	–	–	–	–	–	–	–
P11	R11	–	VDDSDMMC	power	VDDSDMMC	I	–	–	–	–	–	–	–
R11	R12	–	GNDSDMMC	ground	GNDSDMMC	I	–	–	–	–	–	–	–
F4	–	–	VDDISC	power	VDDISC	I	–	–	–	–	–	–	–
G4	–	–	GNDISC	ground	GNDISC	I	–	–	–	–	–	–	–
M12	R17	K11	VDDFUSE	power	VDDFUSE	I	–	–	–	–	–	–	–
U4	V5	P3	VDDPLLA	power	VDDPLLA	I	–	–	–	–	–	–	–
U5	U6	P4	GNDPLLA	ground	GNDPLLA	I	–	–	–	–	–	–	–
T3	M7	K6	VDDAUDIOPLL	power	VDDAUDIOPLL	I	–	–	–	–	–	–	–
T5	P7	L6	GNDDPLL	ground	GNDDPLL	I	–	–	–	–	–	–	–
T4	N6	J6	GNDAUDIOPLL	ground	GNDAUDIOPLL	I	–	–	–	–	–	–	–
U3	M8	J7	VDDAUDIOPLL	–	CLK_AUDIO	O	–	–	–	–	–	–	–
U7	V7	P5	VDDOSC	–	XIN	I	–	–	–	–	–	–	–
U6	V6	P6	VDDOSC	–	XOUT	O	–	–	–	–	–	–	–
T7	R8	N5	VDDOSC	power	VDDOSC	I	–	–	–	–	–	–	–
T6	U5	N6	GNDOSC	ground	GNDOSC	I	–	–	–	–	–	–	–
P8	N8	K7	VDDUTMII	power	VDDUTMII	I	–	–	–	–	–	–	–
R9	P9	–	VDDHSIC	power	VDDHSIC	I	–	–	–	–	–	–	–
P9	N9	L8	GNDUTMII	ground	GNDUTMII	I	–	–	–	–	–	–	–
T8	U8	N7	VDDUTMII	–	HHSDPA	I/O	–	–	–	–	–	–	–
R8	V8	P7	VDDUTMII	–	HHSDMA	I/O	–	–	–	–	–	–	–
U8	U9	N8	VDDUTMII	–	HHSDPB	I/O	–	–	–	–	–	–	–
U9	V9	P8	VDDUTMII	–	HHSDMB	I/O	–	–	–	–	–	–	–
T9	U10	–	VDDHSIC	–	HHSDPDATC	I/O	–	–	–	–	–	–	–
U10	V10	–	VDDHSIC	–	HHSDMSTRC	I/O	–	–	–	–	–	–	–
P7	P8	M7	VDDUTMIC	power	VDDUTMIC	I	–	–	–	–	–	–	–
R7	U7	M8	GNDUTMIC	ground	GNDUTMIC	I	–	–	–	–	–	–	–
T10	N10	–	VDDSDMMC	–	SDCAL	I	–	–	–	–	–	–	–
R6	R7	L7	VDDUTMIC	–	VBG	I	–	–	–	–	–	–	–
P3	P4	M2	VDDBU	–	TST	I	–	–	–	–	–	–	–
U2	V1	N3	VDDBU	–	NRST⁽³⁾	I	–	–	–	–	–	–	–
T2	V2	L4	VDDBU	–	JTAGSEL	I	–	–	–	–	–	–	–
P4	R5	P1	VDDBU	–	WKUP	I	–	–	–	–	–	–	–
N4	U2	–	VDDBU	–	RXD	I	–	–	–	–	–	–	–
R1	U1	N1	VDDBU	–	SHDN	O	–	–	–	–	–	–	–
R3	R6	K5	VDDBU	–	PIOBU0	I/O	–	–	–	–	–	–	–
N8	R4	L3	VDDBU	–	PIOBU1	I/O	–	–	–	–	–	–	–
R2	–	M3	VDDBU	–	PIOBU2	I/O	–	–	–	–	–	–	–
R5	–	N4	VDDBU	–	PIOBU3	I/O	–	–	–	–	–	–	–
R4	–	L5	VDDBU	–	PIOBU4	I/O	–	–	–	–	–	–	–
P5	–	M6	VDDBU	–	PIOBU5	I/O	–	–	–	–	–	–	–
P6	–	–	VDDBU	–	PIOBU6	I/O	–	–	–	–	–	–	–
M8	–	–	VDDBU	–	PIOBU7	I/O	–	–	–	–	–	–	–
N7	U3	M4	VDDBU	power	VDDBU	I	–	–	–	–	–	–	–
N6	U4	M5	GNDBU	ground	GNDBU	I	–	–	–	–	–	–	–
P1	T2	M1	VDDBU	–	XIN32	I	–	–	–	–	–	–	–
P2	R2	L1	VDDBU	–	XOUT32	O	–	–	–	–	–	–	–
T1	V3	N2	VDDBU	–	COMPP	I	–	–	–	–	–	–	–
U1	V4	P2	VDDBU	–	COMPN	I	–	–	–	–	–	–	–

Note:

Signal = ‘PIO’ if GPIO; Dir = Direction; PU = Pull-up; PD = Pull-down; HiZ = High impedance; ST = Schmitt Trigger
The GPIO reset state is not guaranteed during the power-up phase. During this phase, the GPIOs are in Input Pull-Up mode and they take their reset value only after VDDCORE POR reset has been released. If a GPIO must be at level zero at power-up, it is recommended to connect an external pull-down to ensure this state.
For NRST usage, refer to the document SAMA5D2 Hardware Design Considerations.
JTAG boundary scan is available only on JTAG IO Set 1.

The SAMA5D23 is not pin-to-pin compatible with SAMA5D21/SAMA5D22. The table below provides the differences in pinout.

Table 6-3. Pin Description (SAMA5D23 pins different from those in table Pin Description (all packages))
196-pin BGA	Power Rail	I/O Type	Primary		Alternate		PIO Peripheral				Reset State (Signal, Dir, PU, PD, HiZ, ST)⁽¹⁾⁽²⁾
196-pin BGA	Power Rail	I/O Type	Signal	Dir	Signal	Dir	Func	Signal	Dir	IO Set	Reset State (Signal, Dir, PU, PD, HiZ, ST)⁽¹⁾⁽²⁾
N4	GNDBU	ground	GNDBU	I	–	–	–	–	–	–	–
M6	GNDDPLL	ground	GNDDPLL	I	–	–	–	–	–	–	–
M3	JTAGSEL	–	JTAGSEL	I	–	–	–	–	–	–	–
K11	VDDIOP1	GPIO	PA31	I/O	–	–	B	NCS3	O	1	PIO, I, PU, ST
							C	SPI0_MISO	I/O	2
							D	PWML0	O	1
							F	CLASSD_L3	O	1
D6	VDDIOP0	GPIO	PB0	I/O	–	–	B	A21/NANDALE	O	1	PIO, I, PU, ST
							C	SPI0_MOSI	I/O	2
							D	PWMH1	O	1
A6	VDDIOP0	GPIO	PB2	I/O	–	–	B	NRD/NANDOE	O	1	PIO, I, PU, ST
							D	PWMFI0	I	1
							F	CLASSD_R1	O	1
B6	VDDIOP0	GPIO	PB3	I/O	–	–	A	URXD4	I	1	PIO, I, PU, ST
							B	D8	I/O	1
							C	IRQ	I	3
							D	PWMEXTRG1	I	1
							F	CLASSD_R2	O	1
B5	VDDIOP0	GPIO_QSPI	PB5	I/O	–	–	A	TCLK2	I	1	PIO, I, PU, ST
							B	D10	I/O	1
							C	PWMH2	O	1
							D	QSPI1_SCK	O	2
							F	GTSUCOMP	O	3
M12	VDDIOP1	GPIO	PC0	I/O	–	–	A	LCDDAT21	O	1	PIO, I, PU, ST
							B	A23	O	1
							C	FLEXCOM0_IO4	O	1
							D	TWCK0	I/O	1
							F	ISC_D6	I	3
M13	VDDIOP1	GPIO	PC1	I/O	–	–	A	LCDDAT22	O	1	PIO, I, PU, ST
							B	A24	O	1
							C	CANTX0	O	1
							D	SPI1_SPCK	I/O	1
							E	I2SC0_CK	I/O	1
							F	ISC_D7	I	3
L4	VDDBU	–	PIOBU1	I/O	–	–	–	–	–	–	–
L3	VDDBU	–	PIOBU2	I/O	–	–	–	–	–	–	–
M5	VDDBU	–	PIOBU3	I/O	–	–	–	–	–	–	–
L6	VDDBU	–	PIOBU5	I/O	–	–	–	–	–	–	–
P13	VDDFUSE	power	VDDFUSE	I	–	–	–	–	–	–	–

Note:

Signal = ‘PIO’ if GPIO; Dir = Direction; PU = Pull-up; PD = Pull-down; HiZ = High impedance; ST = Schmitt Trigger.
The GPIO reset state is not guaranteed during the power-up phase. During this phase, the GPIOs are in Input Pull-Up mode and they take their reset value only after VDDCORE POR reset has been released. If a GPIO must be at level zero at power-up, it is recommended to connect an external pull-down to ensure this state.

The SAMA5D28B/C are not pin-to-pin compatible with SAMA5D28A, SAMA5D26A/B/C and SAMA5D27A/B/C. The table below provides the differences in pinout.

Table 6-4. Pin Description (SAMA5D28B/C pins different from those in the table Pin Description (all packages))
289-pin BGA	Power Rail	I/O Type	Primary		Alternate		PIO Peripheral				Reset State (Signal, Dir, PU, PD, HiZ, ST)⁽¹⁾⁽²⁾
289-pin BGA	Power Rail	I/O Type	Signal	Dir	Signal	Dir	Func	Signal	Dir	IO Set	Reset State (Signal, Dir, PU, PD, HiZ, ST)⁽¹⁾⁽²⁾
P4	VDDCORE	power	VDDCORE	I	–	–	–	–	–	–	–
N5	GNDCORE	ground	GNDCORE	I	–	–	–	–	–	–	–
R2	VDDBU	–	WKUP	I	–	–	–	–	–	–	–
N6	VDDBU	–	PIOBU0	I/O	–	–	–	–	–	–	–
M8	VDDBU	–	PIOBU2	I/O	–	–	–	–	–	–	–
P6	VDDBU	–	PIOBU3	I/O	–	–	–	–	–	–	–
P5	VDDBU	–	PIOBU4	I/O	–	–	–	–	–	–	–
R5	VDDBU	–	PIOBU5	I/O	–	–	–	–	–	–	–
N7	VDDBU	–	PIOBU6	I/O	–	–	–	–	–	–	–
M5	VDDBU	–	PIOBU7	I/O	–	–	–	–	–	–	–
R3	VDDBU	power	VDDBU	I	–	–	–	–	–	–	–
R4	GNDBU	ground	GNDBU	I	–	–	–	–	–	–	–

Note:

Signal = ‘PIO’ if GPIO; Dir = Direction; PU = Pull-up; PD = Pull-down; HiZ = High impedance; ST = Schmitt Trigger.
The GPIO reset state is not guaranteed during the power-up phase. During this phase, the GPIOs are in Input Pull-Up mode and they take their reset value only after VDDCORE POR reset has been released. If a GPIO must be at level zero at power-up, it is recommended to connect an external pull-down to ensure this state.

SAMA5D2 Series

6.2 Pinouts