30.6.2 RXLP Mode Register
Name: | RXLP_MR |
Offset: | 0x0004 |
Reset: | 0x00000000 |
Property: | Read/Write |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
PAR[2:0] | |||||||||
Access | R/W | R/W | R/W | ||||||
Reset | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
FILTER | |||||||||
Access | R/W | ||||||||
Reset | 0 |
Bits 11:9 – PAR[2:0] Parity Type
Value | Name | Description |
---|---|---|
0 | EVEN | Even parity |
1 | ODD | Odd parity |
2 | SPACE | Parity forced to 0 |
3 | MARK | Parity forced to 1 |
4 | NO | No parity |
Bit 4 – FILTER Receiver Digital Filter
Value | Name | Description |
---|---|---|
0 | DISABLED | RXLP does not filter the receive line. |
1 | ENABLED | RXLP filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). |