The flowcharts shown in this section provide examples for read and
write operations. A polling or interrupt method can be used to check the status bits. The
interrupt method requires that the Interrupt Enable register (FLEX_TWI_IER) be configured
first.
Figure 46-96. TWI Write Operation with Single Data Byte without Internal
AddressFigure 46-97. TWI Write Operation with Single Data Byte and Internal
AddressFigure 46-98. TWI Write Operation with Multiple Data Bytes with or without
Internal AddressFigure 46-99. SMBus Write Operation with Multiple Data Bytes with or
without Internal Address and PEC SendingFigure 46-100. SMBus Write Operation with Multiple Data Bytes with PEC and
Alternative Command ModeFigure 46-101. TWI Write Operation with Multiple Data Bytes and Read
Operation with Multiple Data Bytes (Sr)Figure 46-102. TWI Write Operation with Multiple Data Bytes + Read Operation
and Alternative Command Mode + PECFigure 46-103. TWI Read Operation with Single Data Byte without Internal
AddressFigure 46-104. TWI Read Operation with Single Data Byte and Internal
AddressFigure 46-105. TWI Read Operation with Multiple Data Bytes with or without
Internal AddressFigure 46-106. TWI Read Operation with Multiple Data Bytes with or without
Internal Address with PECFigure 46-107. TWI Read Operation with Multiple Data Bytes with Alternative
Command Mode with PECFigure 46-108. TWI Read Operation with Multiple Data Bytes + Write Operation
with Multiple Data Bytes (Sr)Figure 46-109. TWI Read Operation with Multiple Data Bytes + Write with
Alternative Command Mode with PEC