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Ultra-Low-Power Arm® Cortex®-A5 Core-Based MPU, 500 MHz, Graphics Interface, Ethernet 10/100, CAN, USB, PCI 5.0 Pre-Certified SAMA5D2 Series
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48
Serial Peripheral Interface (SPI)
48.7
Functional Description
48.7.7
FIFOs
SAMA5D2 Series
Introduction
Features
Description
1
Configuration Summary
2
Block Diagram
3
Signal Description
4
Microchip Recommended Power Management Solutions
5
Safety and Security Features
6
Package and Pinout
7
Power Considerations
8
Memories
9
Event System
10
System Controller
11
Peripherals
12
Chip Identifier (CHIPID)
13
Cortex-A5 Processor (ARM)
14
L2 Cache Controller (L2CC)
15
Debug and Test Features
16
Standard Boot Strategies
17
CPU System Bus Matrix (CPUMX)
18
Matrix (H64MX/H32MX)
19
Special Function Registers (SFR)
20
Special Function Registers Backup (SFRBU)
21
Advanced Interrupt Controller (AIC)
22
Watchdog Timer (WDT)
23
Reset Controller (RSTC)
24
Shutdown Controller (SHDWC)
25
Periodic Interval Timer (PIT)
26
Real-time Clock (RTC)
27
System Controller Write Protection (SYSCWP)
28
Slow Clock Controller (SCKC)
29
Peripheral Touch Controller (PTC)
30
Low Power Asynchronous Receiver (RXLP)
31
Clock Generator
32
Power Management Controller (PMC)
33
Parallel Input/Output Controller (PIO)
34
External Memories
35
DDR-SDRAM Controller (MPDDRC)
36
Static Memory Controller (SMC)
37
DMA Controller (XDMAC)
38
LCD Controller (LCDC)
39
Ethernet MAC (GMAC)
40
USB Device High Speed Port (UDPHS)
41
USB Host High Speed Port (UHPHS)
42
Audio Class D Amplifier (CLASSD)
43
Inter-IC Sound Controller (I2SC)
44
Synchronous Serial Controller (SSC)
45
Two-wire Interface (TWIHS)
46
Flexible Serial Communication Controller (FLEXCOM)
47
Universal Asynchronous Receiver Transmitter (UART)
48
Serial Peripheral Interface (SPI)
48.1
Description
48.2
Embedded Characteristics
48.3
Block Diagram
48.4
Application Block Diagram
48.5
Signal Description
48.6
Product Dependencies
48.7
Functional Description
48.7.1
Modes of Operation
48.7.2
Data Transfer
48.7.3
Host Mode Operations
48.7.4
SPI Client Mode
48.7.5
SPI Comparison Function on Received Character
48.7.6
Asynchronous and Partial Wake-Up
48.7.7
FIFOs
48.7.7.1
Overview
48.7.7.2
Sending Data with FIFO Enabled
48.7.7.3
Receiving Data with FIFO Enabled
48.7.7.4
Clearing/Flushing FIFOs
48.7.7.5
TXEMPTY, TDRE and RDRF Behavior
48.7.7.6
Single Data Mode
48.7.7.7
Multiple Data Mode
48.7.7.8
FIFO Pointer Error
48.7.7.9
FIFO Thresholds
48.7.7.10
FIFO Flags
48.7.8
Local Loopback Test Mode
48.7.9
Register Write Protection
48.8
Register Summary
49
Quad Serial Peripheral Interface (QSPI)
50
Secure Digital MultiMedia Card Controller (SDMMC)
51
Image Sensor Controller (ISC)
52
Controller Area Network (MCAN)
53
Timer Counter (TC)
54
Pulse Density Modulation Interface Controller (PDMIC)
55
Pulse Width Modulation Controller (PWM)
56
Secure Fuse Controller (SFC)
57
Integrity Check Monitor (ICM)
58
Advanced Encryption Standard Bridge (AESB)
59
Advanced Encryption Standard (AES)
60
Secure Hash Algorithm (SHA)
61
Triple Data Encryption Standard (TDES)
62
True Random Number Generator (TRNG)
63
Analog Comparator Controller (ACC)
64
Security Module (SECUMOD)
65
Analog-to-Digital Controller (ADC)
66
Electrical Characteristics
67
Mechanical Characteristics
68
Marking
69
Ordering Information
70
Revision History
Microchip Information
48.7.7 FIFOs
