43.6.5 Serial Clock and Word Select Generation

The generation of clocks in the I2SC is described in figure I2SC Clock Generation.

In Client mode, the serial clock and word select clock are driven by an external host. I2SC_CK and I2SC_WS pins are inputs.

In Host mode, the user can configure the main system bus clock, serial clock, and word select clock through I2SC_MR. I2SC_MCK, I2SC_CK, and I2SC_WS pins are outputs and MCK is used to derive the I2SC clocks.

In Host mode, if the peripheral clock frequency is higher than 96 MHz, GCLK[PID] from the PMC must be selected as the I2SC input clock by writing a ’1’ in the CLKSELx bit of the SFR_I2SCLKSEL register located in SFR.

Audio codecs connected to the I2SC pins may require a main system bus clock (I2SC_MCK) signal with a frequency multiple of the audio sample frequency (fs), such as 256fs. When the I2SC is in Host mode, writing a ’1’ to I2SC_MR.IMCKMODE outputs MCK as main system bus clock to the I2SC_MCK pin, and divides MCK to create the internal bit clock, output on the I2SC_CK pin. The clock division factor is defined by writing to I2SC_MR.IMCKFS and I2SC_MR.DATALENGTH, as described in the I2SC_MR.IMCKFS description.

The main system bus clock (I2SC_MCK) frequency is (2×16 × (IMCKFS + 1)) / (IMCKDIV + 1) times the sample frequency (fs), i.e., I2SC_WS frequency.

Example: If the sampling rate is 44.1 kHz with an I2S main system bus clock (I2SC_MCK) ratio of 256, the core frequency must be an integer multiple of 11.2896 MHz. Assuming an integer multiple of 4, the IMCKDIV field must be configured to 4; the field IMCKFS must then be set to 31.

The serial clock (I2SC_CK) frequency is 2 × Slot Length times the sample frequency (fs), where Slot Length is defined in table Slot Length.

Table 43-2. Slot Length
I2SC_MR.DATALENGTH Word Length Slot Length
0 32 bits 32
1 24 bits 32 if I2SC_MR.IWS = 0

24 if I2SC_MR.IWS = 1
2 20 bits
3 18 bits
4 16 bits 16
5 16 bits compact stereo
6 8 bits 8
7 8 bits compact stereo
Warning: I2SC_MR.IMCKMODE must be written to ’1’ if the main system bus clock frequency is strictly higher than the serial clock.

If a main system bus clock output is not required, the MCK clock is used as I2SC_CK by clearing I2SC_MR.IMCKMODE. Alternatively, if the frequency of the MCK clock used is a multiple of the required I2SC_CK frequency, the I2SC_MCK to I2SC_CK divider can be used with the ratio defined by writing the I2SC_MR.IMCKFS field.

The I2SC_WS pin is used as word select as described in section I2S Reception and Transmission Sequence.

Figure 43-3. I2SC Clock Generation