18.3.3 Host to Client Access

The following table shows how hosts and clients interconnect. Writing in a register or field not dedicated to a host or a client has no effect.

Table 18-3. Host to Client Access on H64MX
HOST
0 1 2 3 4 5 6 7 8 9 10 11
CLIENT Bridge from
CPUMX
(Core) XDMAC0 XDMAC1 LCDC DMA SDMMC0
DMA SDMMC1
DMA ISC DMA AESB Bridge
from
H32MX
0 Bridge from H64MX to H32MX X X X X X
1 H64MX Peripheral Bridge X X X X X X
SDMMC0–SDMMC1 X X X X X X
2 DDR2 Port 0 X(1)
3 DDR2 Port 1 X
4 DDR2 Port 2 X
5 DDR2 Port 3 X
6 DDR2 Port 4 X X X
7 DDR2 Port 5 X X
8 DDR2 Port 6 X X
9 DDR2 Port 7 X
10 Internal SRAM X X X X X X X X X X X
11 L2C SRAM X X X X X X X X X X X
12 QSPI0 X X X X X X(1) X
13 QSPI1 X X X X X X(1) X
14 AESB X X X X X X
Note:
  1. To avoid deadlock when accessing the AESB client, the QSPI0, QSPI1 and DDR2 Port 0 client Configuration registers (MATRIX_SCFGx) must be configured either with DEFMSTR_TYPE = NONE ('0') or with DEFMSTR_TYPE = FIXED ('2') and FIXED_DEFMSTR = 10.