54.7.8 PDMIC DSP Configuration Register 0
This register can only be written if the WPEN bit is cleared in the PDMIC Write Protection Mode Register.
| Name: | PDMIC_DSPR0 |
| Offset: | 0x58 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SHIFT[3:0] | SCALE[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| OSR[2:0] | SIZE | SINBYP | HPFBYP | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bits 15:12 – SHIFT[3:0] Data Shift
Shifts the scaled result by SHIFT bits to the right.
Bits 11:8 – SCALE[3:0] Data Scale
Shifts the multiplication operation result by SCALE bits to the right.
Bits 6:4 – OSR[2:0] Global Oversampling Ratio
| Value | Name | Description |
|---|---|---|
| 0 | 128 | Global Oversampling ratio is 128 (SINC filter oversampling ratio is 64) |
| 1 | 64 | Global Oversampling ratio is 64 (SINC filter oversampling ratio is 32) |
Bit 3 – SIZE Data Size
| Value | Description |
|---|---|
| 0 | Converted data size is 16 bits. |
| 1 | Converted data size is 32 bits. |
Bit 2 – SINBYP SINCC Filter Bypass
| Value | Description |
|---|---|
| 0 | Droop compensation filter enabled. |
| 1 | Bypasses the droop compensation filter. |
Bit 1 – HPFBYP High-Pass Filter Bypass
| Value | Description |
|---|---|
| 0 | High-pass filter enabled. |
| 1 | Bypasses the high-pass filter. |