35.7.27 MPDDRC Monitor Information Port x Register (TOTAL_LATENCY)

Name: MPDDRC_MINFOx (TOTAL_LATENCY)
Offset: 0x84 + x*0x04 [x=0..7]
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
 Px_TOTAL_LATENCY[31:24] 
Access RRRRRRRR 
Reset 00000000 
Bit 2322212019181716 
 Px_TOTAL_LATENCY[23:16] 
Access RRRRRRRR 
Reset 00000000 
Bit 15141312111098 
 Px_TOTAL_LATENCY[15:8] 
Access RRRRRRRR 
Reset 00000000 
Bit 76543210 
 Px_TOTAL_LATENCY[7:0] 
Access RRRRRRRR 
Reset 00000000 

Bits 31:0 – Px_TOTAL_LATENCY[31:0] Total Latency on Port x

Can be read if the INFO field is set to 2.

Reports the total latency within an interval (ADDR_HIGH_PORT and ADDR_LOW_PORT) when the port is used.