13.6.1 About the MMU

The MMU works with the L1 and L2 memory system to translate virtual addresses to physical addresses. It also controls accesses to and from external memory.

The ARM v7 Virtual Memory System Architecture (VMSA) features include the following:

  • Page table entries that support:
    • 16 Mbyte supersections. The processor supports supersections that consist of 16 Mbyte blocks of memory.
    • 1 Mbyte sections
    • 64 Kbyte large pages
    • 4 Kbyte small pages
  • 16 access domains
  • Global and application-specific identifiers to remove the requirement for context switch TLB flushes.
  • Extended permissions checking capability.

TLB maintenance and configuration operations are controlled through a dedicated coprocessor, CP15, integrated with the core. This coprocessor provides a standard mechanism for configuring the L1 memory system.

See the ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition for a full architectural description of the ARMv7 VMSA.