32.22.24 PMC Peripheral Clock Enable Register 1
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
Name: | PMC_PCER1 |
Offset: | 0x0100 |
Reset: | – |
Property: | Write-only |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
PID63 | PID62 | PID61 | PID60 | PID59 | PID58 | PID57 | PID56 | ||
Access | W | W | W | W | W | W | W | W | |
Reset | – | – | – | – | – | – | – | – |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
PID55 | PID54 | PID53 | PID52 | PID51 | PID50 | PID49 | PID48 | ||
Access | W | W | W | W | W | W | W | W | |
Reset | – | – | – | – | – | – | – | – |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
PID47 | PID46 | PID45 | PID44 | PID43 | PID42 | PID41 | PID40 | ||
Access | W | W | W | W | W | W | W | W | |
Reset | – | – | – | – | – | – | – | – |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
PID39 | PID38 | PID37 | PID36 | PID35 | PID34 | PID33 | PID32 | ||
Access | W | W | W | W | W | W | W | W | |
Reset | – | – | – | – | – | – | – | – |
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – PIDx Peripheral Clock x Enable
Value | Description |
---|---|
0 |
No effect. |
1 |
Enables the corresponding peripheral clock. |