Compliant with Inter-IC Sound (I2S) Bus Specification
Host, Client, and Controller Modes
Client: Data Received/Transmitted
Host: Data Received/Transmitted And
Clocks Generated
Controller: Clocks Generated
Individual Enable and Disable of Receiver, Transmitter and Clocks
Configurable Clock Generator Common to Receiver and Transmitter
Suitable for a Wide Range of Sample Frequencies (fs), Including 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, and 192 kHz
32 fs to 1024 fs Main System Bus Clock Generated for
External Oversampling Data Converters
Support for Multiple Data Formats
32-, 24-, 20-, 18-, 16-, and 8-bit Mono or Stereo Format
16- and 8-bit Compact Stereo Format, with Left and Right Samples Packed in the Same Word to Reduce Data Transfers
DMA Controller Interfaces the Receiver and Transmitter to Reduce Processor Overhead
One DMA Controller Channel for Both Audio Channels
Smart Holding Registers Management to Avoid Audio Channels Mix After Overrun or Underrun
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
