33.7.29 Secure PIO I/O Freeze Configuration Register
Writing this register will only affect I/O lines enabled in the S_PIO_MSKRx.
Name: | S_PIO_IOFRx |
Offset: | 0x103C + x*0x40 [x=0..3] |
Reset: | – |
Property: | Write-only |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
FRZKEY[23:16] | |||||||||
Access | W | W | W | W | W | W | W | W | |
Reset | – | – | – | – | – | – | – | – |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
FRZKEY[15:8] | |||||||||
Access | W | W | W | W | W | W | W | W | |
Reset | – | – | – | – | – | – | – | – |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
FRZKEY[7:0] | |||||||||
Access | W | W | W | W | W | W | W | W | |
Reset | – | – | – | – | – | – | – | – |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
FINT | FPHY | ||||||||
Access | W | W | |||||||
Reset | – | – |
Bits 31:8 – FRZKEY[23:0] Freeze Key
Value | Name | Description |
---|---|---|
0x494F46 | PASSWD |
Writing any other value in this field aborts the write operation of the WPEN bit. |
Bit 1 – FINT Freeze Interrupt Configuration
Only a hardware reset can reset the FINT bit.
Value | Description |
---|---|
0 |
No effect. |
1 |
Freezes the following configuration fields of Secure I/O lines if FRZKEY corresponds to 0x494F46 (“IOF” in ASCII):
|
Bit 0 – FPHY Freeze Physical Configuration
Only a hardware reset can reset the FPHY bit.
Value | Description |
---|---|
0 |
No effect. |
1 |
Freezes the following configuration fields of Secure I/O lines if FRZKEY corresponds to 0x494F46 (“IOF” in ASCII):
|