35.7.8 MPDDRC Memory Device Register


Bit	31	30	29	28	27	26	25	24
	IO_WIDTH[1:0]		DENSITY[3:0]				TYPE[1:0]
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	REV_ID[7:0]
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	MANU_ID[7:0]
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	RL3	WL		DBW		MD[2:0]
Access	R	R		R/W		R/W	R/W	R/W
Reset	0	0		1		0	1	1

Bits 31:30 – IO_WIDTH[1:0] Width of Memory

This field gives the width of the memory. This field is unique to low-power DDR2-SDRAM and low-power DDR3-SDRAM. When Backup mode is used, this information is lost after Backup mode exit.

Value	Name	Description
0	WIDTH_32	The data bus width is 32 bits.
1	WIDTH_16	The data bus width is 16 bits.
2	WIDTH_8	The data bus width is 8 bits.
3	NOT_USED	–

Bits 29:26 – DENSITY[3:0] Density of Memory

This field is unique to low-power DDR2-SDRAM and low-power DDR3-SDRAM. When Backup mode is used, this information is lost after Backup mode exit

This field gives the density of the memory.

Value	Name	Description
0	DENSITY_64MBITS	The device density is 64 Mbits.
1	DENSITY_128MBITS	The device density is 128 Mbits.
2	DENSITY_256MBITS	The device density is 256 Mbits.
3	DENSITY_512MBITS	The device density is 512 Mbits.
4	DENSITY_1GBITS	The device density is 1 Gbit.
5	DENSITY_2GBITS	The device density is 2 Gbits.
6	DENSITY_4GBITS	The device density is 4 Gbits.
7	DENSITY_8GBITS	The device density is 8 Gbits.
8	DENSITY_16GBITS	The device density is 16 Gbits.
9	DENSITY_32GBITS	The device density is 32 Gbits.

Bits 25:24 – TYPE[1:0] DRAM Architecture

This field gives the DRAM architecture. This field is unique to low-power DDR2-SDRAM and low-power DDR3-SDRAM. When Backup mode is used, this information is lost after Backup mode exit.

Value	Name	Description
0	S4_SDRAM	4n prefetch architecture
1	S2_SDRAM	2n prefetch architecture
2	NVM	Non-volatile device
3	S8_SDRAM	8n prefetch architecture

Bits 23:16 – REV_ID[7:0] Revision Identification

This field gives the revision ID. This field is unique to low-power DDR2-SDRAM and low-power DDR3-SDRAM. When Backup mode is used, this information is lost after Backup mode exit.

Bits 15:8 – MANU_ID[7:0] Manufacturer Identification

This field gives information concerning the Manufacturer ID. For more information concerning the Manufacturer ID, Refer to document JC-42.6 “Manufacturer Identification (ID) Code for Low Power Memories”. This field is unique to low-power DDR2-SDRAM and low-power DDR3-SDRAM. When Backup mode is used, this information is lost after Backup mode exit.

Bit 7 – RL3 Read Latency 3 Option Support

This field gives information concerning the read latency supported. Read latency 3 has been defined per Jedec for frequency ≤ 166 MHz. This feature is optional. If the LPDDR3 device does not support this feature, a CAS latency of 6 is used. This field is unique to low-power DDR3-SDRAM. When Backup mode is used, this information is lost after Backup mode exit.

Value	Name	Description
0	RL3_SUPPORT	Read latency of 3 is supported
1	RL3_NOT_SUPPORTED	Read latency of 3 is not supported

Bit 6 – WL Write Latency

This field gives the write latency supported by the memory device. This field is unique to low-power DDR3-SDRAM. When Backup mode is used, this information is lost after Backup mode exit.

Value	Name	Description
0	WL_SETA	Write Latency Set A
1	WL_SETB	Write Latency Set B

Bit 4 – DBW Data Bus Width

Value	Name	Description
0	DBW_32_BITS	Data bus width is 32 bits
1	DBW_16_BITS	Data bus width is 16 bits.

Bits 2:0 – MD[2:0] Memory Device

Value	Name	Description
3	LPDDR_SDRAM	Low-power DDR1-SDRAM
4	DDR3_SDRAM	DDR3-SDRAM
5	LPDDR3_SDRAM	Low-power DDR3-SDRAM
6	DDR2_SDRAM	DDR2-SDRAM
7	LPDDR2_SDRAM	Low-power DDR2-SDRAM

Name:	MPDDRC_MD
Offset:	0x20
Reset:	0x00000013
Property:	Read/Write

SAMA5D2 Series