46.10.25 USART Receiver Timeout Register

This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register.

Name: FLEX_US_RTOR
Offset: 0x224
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
        TO[16] 
Access R/W 
Reset 0 
Bit 15141312111098 
 TO[15:8] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 TO[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 16:0 – TO[16:0] Timeout Value

The TO field size is limited to 8 bits if the ISO7816 logic is not implemented on some instances of FLEXCOM. The ISO7816 logic is implemented if it is possible to write FLEX_US_MR.MAX_ITERATIONS=1 (a read operation must be performed after the write operation to check that MAX_ITERATIONS equals 1).
ValueDescription
0 The receiver timeout is disabled.
1–131071 The receiver timeout is enabled and the timeout delay is TO × bit period.