59.5.6 AES Interrupt Status Register

Name: AES_ISR
Offset: 0x1C
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
      PLENERREOPADTAGRDY 
Access RRR 
Reset 000 
Bit 15141312111098 
 URAT[3:0]   URAD 
Access RRRRR 
Reset 00000 
Bit 76543210 
        DATRDY 
Access R 
Reset 0 

Bit 18 – PLENERR Padding Length Error

ValueDescription
0

No Padding Length Error occurred.
1

Padding Length Error detected.

Bit 17 – EOPAD End of Padding

ValueDescription
0

Padding is not over.
1

Padding phase is over.

Bit 16 – TAGRDY GCM Tag Ready

ValueDescription
0

GCM Tag is not valid.
1

GCM Tag generation is complete (cleared by reading GCM Tag, starting another processing or when writing a new key).

Bits 15:12 – URAT[3:0] Unspecified Register Access (cleared by writing SWRST in AES_CR)

Only the last Unspecified Register Access Type is available through the URAT field.

ValueNameDescription
0 IDR_WR_PROCESSING

Input Data register written during the data processing when SMOD = 2 mode.
1 ODR_RD_PROCESSING

Output Data register read during the data processing.
2 MR_WR_PROCESSING

Mode register written during the data processing.
3 ODR_RD_SUBKGEN

Output Data register read during the sub-keys generation.
4 MR_WR_SUBKGEN

Mode register written during the sub-keys generation.
5 WOR_RD_ACCESS

Write-only register read access.

Bit 8 – URAD Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR)

ValueDescription
0

No unspecified register access has been detected since the last SWRST.
1

At least one unspecified register access has been detected since the last SWRST.

Bit 0 – DATRDY Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx)

Note: If AES_MR.LOD = 1: In Manual and Auto mode, the DATRDY flag can also be cleared by writing at least one AES_IDATARx.
ValueDescription
0

Output data not valid.
1

Encryption or decryption process is completed.