65.7.18 Channel Offset Register

This register can only be written if the WPEN bit is cleared in the ADC Write Protection Mode Register.

Name: ADC_COR
Offset: 0x4C
Reset: 0
Property: Read/Write

Bit 3130292827262524 
     DIFF11DIFF10DIFF9DIFF8 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 2322212019181716 
 DIFF7DIFF6DIFF5DIFF4DIFF3DIFF2DIFF1DIFF0 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
          
Access  
Reset  

Bits 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27 – DIFFx Differential Inputs for Channel x

ValueDescription
0 Corresponding channel is set in Single-ended mode.
1 Corresponding channel is set in Differential mode.