18.1 Description

The system embeds three system bus matrixes, the CPU System Bus Matrix (CPUMX), the 64-bit Matrix (H64MX) and the 32-bit Matrix (H32MX). This section describes the implementation of the H64MX and the H32MX.

For details on the CPUMX matrix, refer to the section “CPU System Bus Matrix (CPUMX)”.

Each matrix implements a multilayer system bus, which enables parallel access paths between multiple hosts and clients in a system, thus increasing the overall bandwidth. The normal latency to connect a host to a client is one cycle, except for the default host of the accessed client which is connected directly (zero cycle latency).

Note: When a host and a client are on different bus matrixes (CPUMX, H64MX, or H32MX), both matrixes (H64MX and H32MX) and the bridge between the bus matrixes must be configured accordingly.