50.12.12 SDMMC Power Control Register
Name: | SDMMC_PCR |
Offset: | 0x29 |
Reset: | 0x0E |
Property: | Read/Write |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
SDBPWR | |||||||||
Access | R/W | ||||||||
Reset | 0 |
Bit 0 – SDBPWR SD Bus Power
This bit is automatically cleared by the SDMMC if the card is removed. If this bit is cleared, the SDMMC stops driving SDMMC_CMD and SDMMC_DAT[7:0] (tri-state) and drives SDMMC_CK to low level.