16.5.8 Hardware and Software Constraints
The table below provides clock frequencies configured by the ROM code during boot.
| Clock | MRL A | MRL B | MRL C |
|---|---|---|---|
| PLLA | 792 MHz | 792 MHz | 756 MHz |
| PCK | 396 MHz | 396 MHz | 378 MHz |
| MCK | 132 MHz | 132 MHz | 126 MHz |
| SDMMC (init/operational) | 400 kHz / 25 MHz | 400 kHz / 25 MHz | 400 kHz / 25 MHz |
| SPI | 6 MHz | 12 MHz | 12 MHz |
| QSPI | 25 MHz | 50 MHz | 50 MHz |
The NVM drivers use several PIOs in Peripheral mode to communicate with external memory devices. Care must be taken when these PIOs are used by the application. The connected devices could be unintentionally driven at boot time, and thus electrical conflicts between the output pins used by the NVM drivers and the connected devices could occur.
To ensure the correct functionality, it is recommended to plug in critical devices to other pins not used by the NVM.
The table below contains a list of pins that are driven during the boot program execution. These pins are driven during the boot sequence for a period of less than 1 second if no correct boot program is found. For MRL C parts only, the drive strength of some I/O pins is set to 'medium' while the pins are used in peripheral mode by the ROM code. For MRL A and B, drive strength is always low.
Before performing the jump to the application in the internal SRAM, all the PIOs and peripherals used in the boot program are set to their reset state.
| NVM Bootloader | Peripheral | IO Set | Pin | PIO Line | Drive Strength (MRL C only) |
|---|---|---|---|---|---|
| SD Card / e.MMC | SDMMC_0 | 1 | SDMMC0_CK | PIOA0 | low |
| SDMMC0_CMD | PIOA1 | medium | |||
| SDMMC0_DAT0 | PIOA2 | medium | |||
| SDMMC0_DAT1 | PIOA3 | medium | |||
| SDMMC0_DAT2 | PIOA4 | medium | |||
| SDMMC0_DAT3 | PIOA5 | medium | |||
| SDMMC0_DAT4 | PIOA6 | low | |||
| SDMMC0_DAT5 | PIOA7 | low | |||
| SDMMC0_DAT6 | PIOA8 | low | |||
| SDMMC0_DAT7 | PIOA9 | low | |||
| SDMMC0_RSTN | PIOA10 | medium | |||
| SDMMC0_1V8SEL | PIOA11 | low | |||
| SDMMC0_WP | PIOA12 | medium | |||
| SDMMC0_CD | PIOA13 | medium | |||
| SDMMC_1 | 1 | SDMMC1_DAT0 | PIOA18 | medium | |
| SDMMC1_DAT1 | PIOA19 | medium | |||
| SDMMC1_DAT2 | PIOA20 | medium | |||
| SDMMC1_DAT3 | PIOA21 | medium | |||
| SDMMC1_CK | PIOA22 | low | |||
| SDMMC1_RSTN | PIOA27 | medium | |||
| SDMMC1_CMD | PIOA28 | medium | |||
| SDMMC1_WP | PIOA29 | medium | |||
| SDMMC1_CD | PIOA30 | medium | |||
| NAND Flash | HSMC | 1 | D0–D7 | PIOA22-PIOA29 | low |
| NANDWE | PIOA30 | low | |||
| NANDCS3 | PIOA31 | low | |||
| NAND ALE | PIOB0 | low | |||
| NAND CLE | PIOB1 | low | |||
| NANDOE | PIOB2 | low | |||
| D8–D15 | PIOB3–PIOB10 | low | |||
| 2 | D0–D7 | PIOA0–PIOA7 | low | ||
| NANDWE | PIOA8 | low | |||
| NANDCS3 | PIOA9 | low | |||
| NAND ALE | PIOA10 | low | |||
| NAND CLE | PIOA11 | low | |||
| NANDOE | PIOA12 | low | |||
| D8–D15 | PA13–PA20 | low | |||
| SPI Flash | SPI_0 | 1 | SPCK | PIOA14 | low |
| MOSI | PIOA15 | low | |||
| MISO | PIOA16 | medium | |||
| NPCS0 | PIOA17 | low | |||
| 2 | NPCS0 | PIOA30 | low | ||
| MISO | PIOA31 | medium | |||
| MOSI | PIOB0 | low | |||
| SPCK | PIOB1 | low | |||
| SPI_1 | 1 | SPCK | PIOC1 | low | |
| MOSI | PIOC2 | low | |||
| MISO | PIOC3 | medium | |||
| NPCS0 | PIOC4 | low | |||
| 2 | SPCK | PIOA22 | low | ||
| MOSI | PIOA23 | low | |||
| MISO | PIOA24 | medium | |||
| NPCS0 | PIOA25 | low | |||
| 3 | SPCK | PIOD25 | low | ||
| MOSI | PIOD26 | low | |||
| MISO | PIOD27 | medium | |||
| NPCS0 | PIOD28 | low | |||
| QSPI Flash | QSPI_0 | 1 | SCK | PIOA0 | low |
| CS | PIOA1 | low | |||
| IO0 | PIOA2 | low | |||
| IO1 | PIOA3 | low | |||
| IO2 | PIOA4 | low | |||
| IO3 | PIOA5 | low | |||
| QSPI_0 | 2 | SCK | PIOA14 | low | |
| CS | PIOA15 | low | |||
| IO0 | PIOA16 | medium | |||
| IO1 | PIOA17 | medium | |||
| IO2 | PIOA18 | medium | |||
| IO3 | PIOA19 | medium | |||
| QSPI_0 | 3 | SCK | PIOA22 | low | |
| CS | PIOA23 | low | |||
| IO0 | PIOA24 | medium | |||
| IO1 | PIOA25 | medium | |||
| IO2 | PIOA26 | medium | |||
| IO3 | PIOA27 | medium | |||
| QSPI_1 | 1 | SCK | PIOA6 | low | |
| CS | PIOA7 | medium | |||
| IO0 | PIOA8 | medium | |||
| IO1 | PIOA9 | medium | |||
| IO2 | PIOA10 | medium | |||
| IO3 | PIOA11 | low | |||
| QSPI_1 | 2 | SCK | PIOB5 | low | |
| CS | PIOB6 | low | |||
| IO0 | PIOB7 | medium | |||
| IO1 | PIOB8 | medium | |||
| IO2 | PIOB9 | medium | |||
| IO3 | PIOB10 | medium | |||
| QSPI_1 | 3 | SCK | PIOB14 | low | |
| CS | PIOB15 | low | |||
| IO0 | PIOB16 | medium | |||
| IO1 | PIOB17 | medium | |||
| IO2 | PIOB18 | medium | |||
| IO3 | PIOB19 | medium | |||
| Console Terminal and SAM-BA Monitor | UART_0 | 1 | DRXD | PIOB26 | low |
| DTXD | PIOB27 | low | |||
| UART_1 | 1 | DRXD | PIOD2 | low | |
| DTXD | PIOD3 | low | |||
| 2 | DRXD | PIOC7 | low | ||
| DTXD | PIOC8 | low | |||
| UART_2 | 1 | DRXD | PIOD4 | low | |
| DTXD | PIOD5 | low | |||
| 2 | DRXD | PIOD23 | low | ||
| DTXD | PIOD24 | low | |||
| 3 | DRXD | PIOD19 | low | ||
| DTXD | PIOD20 | low | |||
| UART_3 | 1 | DRXD | PIOC12 | low | |
| DTXD | PIOC13 | low | |||
| 2 | DRXD | PIOC31 | low | ||
| DTXD | PIOD0 | low | |||
| 3 | DRXD | PIOB11 | low | ||
| DTXD | PIOB12 | low | |||
| UART_4 | 1 | DRXD | PIOB3 | low | |
| DTXD | PIOB4 | low | |||
| Debug Port | JTAG | 1 | TCK | PIOD14 | low |
| TDI | PIOD15 | low | |||
| TDO | PIOD16 | low | |||
| TMS | PIOD17 | low | |||
| NTRST | PIOD18 | low | |||
| 2 | TCK | PIOD6 | low | ||
| TDI | PIOD7 | low | |||
| TDO | PIOD8 | low | |||
| TMS | PIOD9 | low | |||
| NTRST | PIOD10 | low | |||
| 3 | TCK | PIOD27 | low | ||
| TDI | PIOD28 | low | |||
| TDO | PIOD29 | low | |||
| TMS | PIOD30 | low | |||
| NTRST | PIOD31 | low | |||
| 4 | TCK | PIOA22 | low | ||
| TDI | PIOA23 | low | |||
| TDO | PIOA24 | low | |||
| TMS | PIOA25 | low | |||
| NTRST | PIOA26 | low |