24.7.3 SHDWC Status Register

Note: The events are detected only when the system is in Backup mode.
Name: SHDW_SR
Offset: 0x08
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
       WKUPIS9WKUPIS8 
Access RR 
Reset 00 
Bit 2322212019181716 
 WKUPIS7WKUPIS6WKUPIS5WKUPIS4WKUPIS3WKUPIS2WKUPIS1WKUPIS0 
Access RRRRRRRR 
Reset 00000000 
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
 RXLPWKACCWKRTCWK    WKUPS 
Access RRRR 
Reset 0000 

Bits 16, 17, 18, 19, 20, 21, 22, 23, 24, 25 – WKUPISx Wake-up x Input Status

Note: WKUPIS1 reports the status of the Security Module event.
ValueNameDescription
0 DISABLE

The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.

1 ENABLE

The corresponding wake-up input was active at the time the debouncer triggered a wake-up event.

Bit 7 – RXLPWK Debug Unit Wake-up

ValueDescription
0

No wake-up alarm from the Backup RX UART Comparison unit (RXLP) occurred since the last read of SHDW_SR.

1

At least one wake-up alarm from the Backup RX UART Comparison unit (RXLP) occurred since the last read of SHDW_SR.

Bit 6 – ACCWK Analog Comparator Controller Wake-up

ValueDescription
0

No wake-up alarm from the ACC occurred since the last read of SHDW_SR.

1

At least one wake-up alarm from the ACC occurred since the last read of SHDW_SR.

Bit 5 – RTCWK Real-time Clock Wake-up

ValueDescription
0

No wake-up alarm from the RTC occurred since the last read of SHDW_SR.

1

At least one wake-up alarm from the RTC occurred since the last read of SHDW_SR.

Bit 0 – WKUPS PIOBU, WKUP Wake-up Status

ValueNameDescription
0 NO

No wake-up due to the assertion of PIOBU, WKUP pins has occurred since the last read of SHDW_SR.

1 PRESENT

At least one wake-up due to the assertion of PIOBU, WKUP pins has occurred since the last read of SHDW_SR.