21.8.2 Interrupt Latencies

Global interrupt latencies depend on several parameters, including:

• The time the software masks the interrupts
• Occurrence, either at the processor level or at the AIC level
• The execution time of the instruction in progress when the interrupt occurs
• The treatment of higher priority interrupts and the resynchronization of the hardware signals

This section addresses hardware resynchronizations only. It gives details about the latency times between the events on an external interrupt leading to a valid interrupt (edge or level) or the assertion of an internal interrupt source and the assertion of the nIRQ or nFIQ line on the processor. The resynchronization time depends on the programming of the interrupt source and on its type (internal or external). For the standard interrupt, resynchronization times are given assuming there is no higher priority in progress.

The PIO Controller multiplexing has no effect on the interrupt latencies of the external interrupt sources.