46.10.4 USART Control Register

For SPI control, see USART Control Register (SPI_MODE).

Name: FLEX_US_CR
Offset: 0x200
Reset: 
Property: Write-only

Bit 3130292827262524 
 FIFODISFIFOEN REQCLR TXFLCLRRXFCLRTXFCLR 
Access WWWWWW 
Reset  
Bit 2322212019181716 
   LINWKUPLINABTRTSDISRTSEN   
Access WWWW 
Reset  
Bit 15141312111098 
 RETTORSTNACKRSTITSENDASTTTOSTPBRKSTTBRKRSTSTA 
Access WWWWWWWW 
Reset  
Bit 76543210 
 TXDISTXENRXDISRXENRSTTXRSTRX   
Access WWWWWW 
Reset  

Bit 31 – FIFODIS FIFO Disable

ValueDescription
0 No effect.
1 Disables the Transmit and Receive FIFOs.

Bit 30 – FIFOEN FIFO Enable

ValueDescription
0 No effect.
1 Enables the Transmit and Receive FIFOs.

Bit 28 – REQCLR Request to Clear the Comparison Trigger

ValueDescription
0 No effect.
1 Restarts the comparison trigger to enable FLEX_US_RHR loading.

Bit 26 – TXFLCLR Transmit FIFO Lock CLEAR

ValueDescription
0 No effect.
1 Clears the Transmit FIFO Lock.

Bit 25 – RXFCLR Receive FIFO Clear

ValueDescription
0 No effect.
1 Empties the Receive FIFO.

Bit 24 – TXFCLR Transmit FIFO Clear

ValueDescription
0 No effect.
1 Empties the Transmit FIFO.

Bit 21 – LINWKUP Send LIN Wakeup Signal

ValueDescription
0 No effect:
1 Sends a wakeup signal on the LIN bus.

Bit 20 – LINABT Abort LIN Transmission

ValueDescription
0 No effect.
1 Aborts the current LIN transmission.

Bit 19 – RTSDIS Request to Send Disable

ValueDescription
0 No effect.
1 Drives the RTS pin to 0 if FLEX_US_MR.USART_MODE field = 2, else drives the RTS pin to 1 if FLEX_US_MR.USART_MODE field = 0.

Bit 18 – RTSEN Request to Send Enable

ValueDescription
0 No effect.
1 Drives the RTS pin to 1 if FLEX_US_MR.USART_MODE field = 2, else drives the RTS pin to 0 if FLEX_US_MR.USART_MODE field = 0.

Bit 15 – RETTO Start Timeout Immediately

ValueDescription
0 No effect
1 Immediately restarts timeout period.

Bit 14 – RSTNACK Reset Non Acknowledge

ValueDescription
0 No effect
1 Resets FLEX_US_CSR.NACK.

Bit 13 – RSTIT Reset Iterations

ValueDescription
0 No effect.
1 Resets FLEX_US_CSR.ITER. No effect if the ISO7816 is not enabled.

Bit 12 – SENDA Send Address

ValueDescription
0 No effect.
1 In Multidrop mode only, the next character written to FLEX_US_THR is sent with the address bit set.

Bit 11 – STTTO Clear TIMEOUT Flag and Start Timeout After Next Character Received

ValueDescription
0 No effect.
1 Starts waiting for a character before clocking the timeout counter. Immediately disables a timeout period in progress. Resets the FLEX_US_CSR.TIMEOUT status bit.

Bit 10 – STPBRK Stop Break

ValueDescription
0 No effect.
1 Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods. No effect if no break is being transmitted.

Bit 9 – STTBRK Start Break

ValueDescription
0 No effect.
1 Starts transmission of a break after the characters present in FLEX_US_THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted.

Bit 8 – RSTSTA Reset Status Bits

ValueDescription
0 No effect.
1 Resets the PARE, FRAME, OVRE, MANE, LINBE, LINISFE, LINIPE, LINCE, LINSNRE, LINSTE, LINHTE, LINID, LINTC, LINBK, CMP and RXBRK in FLEX_US_CSR status bits, as well as the TXFEF, TXFFF, TXFTHF, RXFEF, RXFFF, RXFTHF, TXFPTEF, RXFPTEF in FLEX_US_FESR status bits.

Bit 7 – TXDIS Transmitter Disable

ValueDescription
0 No effect.
1 Disables the transmitter.

Bit 6 – TXEN Transmitter Enable

ValueDescription
0 No effect.
1 Enables the transmitter if TXDIS is 0.

Bit 5 – RXDIS Receiver Disable

ValueDescription
0 No effect.
1 Disables the receiver.

Bit 4 – RXEN Receiver Enable

ValueDescription
0 No effect.
1 Enables the receiver, if RXDIS is 0.

Bit 3 – RSTTX Reset Transmitter

ValueDescription
0 No effect.
1 Resets the transmitter.

Bit 2 – RSTRX Reset Receiver

ValueDescription
0 No effect.
1 Resets the receiver.