65.7.2 ADC Mode Register
This register can only be written if the WPEN bit is cleared in the ADC Write Protection Mode Register.
| Name: | ADC_MR |
| Offset: | 0x04 |
| Reset: | 0x20000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| USEQ | MAXSPEED | TRANSFER[1:0] | TRACKTIM[3:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| ANACH | STARTUP[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PRESCAL[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FWUP | SLEEP | TRGSEL[2:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
Bit 31 – USEQ User Sequence Enable
| Value | Name | Description |
|---|---|---|
| 0 | NUM_ORDER | Normal mode: the controller converts channels in a simple numeric order depending only on the channel index. |
| 1 | REG_ORDER | User Sequence mode: the sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers and can be used to convert the same channel several times. |
Bit 30 – MAXSPEED Maximum Sampling Rate Enable in Freerun Mode
This bit should always be set to 0.
Bits 29:28 – TRANSFER[1:0] Transfer Time
The TRANSFER field must be set to 2 to guarantee the optimal transfer time.
Bits 27:24 – TRACKTIM[3:0] Tracking Time
| Value | Name | Description |
|---|---|---|
| 0 | ADCCLK6 | The tracking time is 6 ADC clock cycles. |
| 1–14 | – | The tracking time is 6 ADC clock cycles. |
| 15 | ADCCLK7 | The tracking time is 7 ADC clock cycles. |
Bit 23 – ANACH Analog Change
| Value | Name | Description |
|---|---|---|
| 0 | NONE | No analog change on channel switching: DIFF0 is used for all channels. |
| 1 | ALLOWED | Allows different analog settings for each channel. See ADC_COR. |
Bits 19:16 – STARTUP[3:0] Startup Time
| Value | Name | Description |
|---|---|---|
| 0 | SUT0 | 0 periods of ADCCLK |
| 1 | SUT8 | 8 periods of ADCCLK |
| 2 | SUT16 | 16 periods of ADCCLK |
| 3 | SUT24 | 24 periods of ADCCLK |
| 4 | SUT64 | 64 periods of ADCCLK |
| 5 | SUT80 | 80 periods of ADCCLK |
| 6 | SUT96 | 96 periods of ADCCLK |
| 7 | SUT112 | 112 periods of ADCCLK |
| 8 | SUT512 | 512 periods of ADCCLK |
| 9 | SUT576 | 576 periods of ADCCLK |
| 10 | SUT640 | 640 periods of ADCCLK |
| 11 | SUT704 | 704 periods of ADCCLK |
| 12 | SUT768 | 768 periods of ADCCLK |
| 13 | SUT832 | 832 periods of ADCCLK |
| 14 | SUT896 | 896 periods of ADCCLK |
| 15 | SUT960 | 960 periods of ADCCLK |
Bits 15:8 – PRESCAL[7:0] Prescaler Rate Selection
PRESCAL = (fperipheral clock / (2 × fADCCLK)) – 1.
Bit 6 – FWUP Fast Wakeup
| Value | Name | Description |
|---|---|---|
| 0 | OFF | If SLEEP is 1, then both ADC core and reference voltage circuitry are off between conversions. |
| 1 | ON | If SLEEP is 1, then Fast Wakeup Sleep mode: the voltage reference is on between conversions and ADC core is off. |
Bit 5 – SLEEP Sleep Mode
| Value | Name | Description |
|---|---|---|
| 0 | NORMAL | Normal mode: the ADC core and reference voltage circuitry are kept on between conversions. |
| 1 | SLEEP | Sleep mode: the wakeup time can be modified by programming the FWUP bit. |
Bits 3:1 – TRGSEL[2:0] Trigger Selection
| Value | Name | Description |
|---|---|---|
| 0 | ADC_TRIG0 | ADTRG |
| 1 | ADC_TRIG1 | TIOA0 |
| 2 | ADC_TRIG2 | TIOA1 |
| 3 | ADC_TRIG3 | TIOA2 |
| 4 | ADC_TRIG4 | PWM event line 0 |
| 5 | ADC_TRIG5 | PWM event line 1 |
| 6 | ADC_TRIG6 | TIOA3 |
| 7 | ADC_TRIG7 | RTCOUT0 |