18.13.5 Host Error Interrupt Enable Register

This register can only be written if the WPEN bit is cleared in the Write Protection Mode Register.

Name: MATRIX_MEIER
Offset: 0x0150
Reset: 
Property: Write-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
     MERR11MERR10MERR9MERR8 
Access WWWW 
Reset  
Bit 76543210 
 MERR7MERR6MERR5MERR4MERR3MERR2MERR1MERR0 
Access WWWWWWWW 
Reset  

Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 – MERRx Host x Access Error

ValueDescription
0

No effect.

1

Enables Host x Access Error interrupt source.